Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1616423076	1613146976	0	0
CheckNGreaterZero_A	4068	4068	0	0
GntImpliesReady_A	1616423076	400471234	0	0
GntImpliesValid_A	1616423076	400471234	0	0
GrantKnown_A	1616423076	1613146976	0	0
IdxKnown_A	1616423076	1613146976	0	0
IndexIsCorrect_A	1616423076	400471234	0	0
NoReadyValidNoGrant_A	1616423076	181021230	0	0
Priority_A	1616423076	423780678	0	0
ReadyAndValidImplyGrant_A	1616423076	400471234	0	0
ReqAndReadyImplyGrant_A	1616423076	400471234	0	0
ReqImpliesValid_A	1616423076	423780678	0	0
ValidKnown_A	1616423076	1613146976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	1613146976	0	0
T1	11844	11352	0	0
T2	230872	230612	0	0
T3	4692	4304	0	0
T4	490948	490700	0	0
T5	362136	357952	0	0
T6	1384548	1384160	0	0
T7	2259816	2259260	0	0
T11	3776	3432	0	0
T12	914028	914020	0	0
T17	11116	10752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4068	4068	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	400471234	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210856	0	0
T5	362136	75068	0	0
T6	1384548	479666	0	0
T7	2259816	35032	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	400471234	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210856	0	0
T5	362136	75068	0	0
T6	1384548	479666	0	0
T7	2259816	35032	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	1613146976	0	0
T1	11844	11352	0	0
T2	230872	230612	0	0
T3	4692	4304	0	0
T4	490948	490700	0	0
T5	362136	357952	0	0
T6	1384548	1384160	0	0
T7	2259816	2259260	0	0
T11	3776	3432	0	0
T12	914028	914020	0	0
T17	11116	10752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	1613146976	0	0
T1	11844	11352	0	0
T2	230872	230612	0	0
T3	4692	4304	0	0
T4	490948	490700	0	0
T5	362136	357952	0	0
T6	1384548	1384160	0	0
T7	2259816	2259260	0	0
T11	3776	3432	0	0
T12	914028	914020	0	0
T17	11116	10752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	400471234	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210856	0	0
T5	362136	75068	0	0
T6	1384548	479666	0	0
T7	2259816	35032	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	181021230	0	0
T1	11844	858	0	0
T2	230872	256	0	0
T3	4692	286	0	0
T4	490948	4942	0	0
T5	362136	256	0	0
T6	1384548	162336	0	0
T7	2259816	1216430	0	0
T11	3776	256	0	0
T12	914028	2110294	0	0
T17	11116	256	0	0
T18	0	106	0	0
T23	0	24	0	0
T35	0	122	0	0
T36	0	162648	0	0
T40	0	1048932	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	423780678	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210892	0	0
T5	362136	75068	0	0
T6	1384548	578550	0	0
T7	2259816	544170	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	400471234	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210856	0	0
T5	362136	75068	0	0
T6	1384548	479666	0	0
T7	2259816	35032	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	400471234	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210856	0	0
T5	362136	75068	0	0
T6	1384548	479666	0	0
T7	2259816	35032	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	423780678	0	0
T1	11844	630	0	0
T2	230872	30662	0	0
T3	4692	84	0	0
T4	490948	210892	0	0
T5	362136	75068	0	0
T6	1384548	578550	0	0
T7	2259816	544170	0	0
T11	3776	412	0	0
T12	914028	1662848	0	0
T17	11116	64	0	0
T18	0	46	0	0
T35	0	84320	0	0
T40	0	826866	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616423076	1613146976	0	0
T1	11844	11352	0	0
T2	230872	230612	0	0
T3	4692	4304	0	0
T4	490948	490700	0	0
T5	362136	357952	0	0
T6	1384548	1384160	0	0
T7	2259816	2259260	0	0
T11	3776	3432	0	0
T12	914028	914020	0	0
T17	11116	10752	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404105769	403286744	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	404105769	109715675	0	0
GntImpliesValid_A	404105769	109715675	0	0
GrantKnown_A	404105769	403286744	0	0
IdxKnown_A	404105769	403286744	0	0
IndexIsCorrect_A	404105769	109715675	0	0
NoReadyValidNoGrant_A	404105769	47578601	0	0
Priority_A	404105769	115495471	0	0
ReadyAndValidImplyGrant_A	404105769	109715675	0	0
ReqAndReadyImplyGrant_A	404105769	109715675	0	0
ReqImpliesValid_A	404105769	115495471	0	0
ValidKnown_A	404105769	403286744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715675	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715675	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715675	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	47578601	0	0
T1	2961	383	0	0
T2	57718	128	0	0
T3	1173	143	0	0
T4	122737	1599	0	0
T5	90534	128	0	0
T6	346137	41037	0	0
T7	564954	323687	0	0
T11	944	128	0	0
T12	228507	530686	0	0
T17	2779	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	115495471	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	130745	0	0
T7	564954	143152	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715675	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715675	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	115495471	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	130745	0	0
T7	564954	143152	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404105769	403286744	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	404105769	109715567	0	0
GntImpliesValid_A	404105769	109715567	0	0
GrantKnown_A	404105769	403286744	0	0
IdxKnown_A	404105769	403286744	0	0
IndexIsCorrect_A	404105769	109715567	0	0
NoReadyValidNoGrant_A	404105769	47578463	0	0
Priority_A	404105769	115495501	0	0
ReadyAndValidImplyGrant_A	404105769	109715567	0	0
ReqAndReadyImplyGrant_A	404105769	109715567	0	0
ReqImpliesValid_A	404105769	115495501	0	0
ValidKnown_A	404105769	403286744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715567	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715567	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715567	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	47578463	0	0
T1	2961	383	0	0
T2	57718	128	0	0
T3	1173	143	0	0
T4	122737	1599	0	0
T5	90534	128	0	0
T6	346137	41037	0	0
T7	564954	323687	0	0
T11	944	128	0	0
T12	228507	530686	0	0
T17	2779	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	115495501	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	130745	0	0
T7	564954	143152	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715567	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	109715567	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	106550	0	0
T7	564954	9491	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	115495501	0	0
T1	2961	299	0	0
T2	57718	8062	0	0
T3	1173	42	0	0
T4	122737	66764	0	0
T5	90534	18842	0	0
T6	346137	130745	0	0
T7	564954	143152	0	0
T11	944	206	0	0
T12	228507	418138	0	0
T17	2779	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404105769	403286744	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	404105769	90519996	0	0
GntImpliesValid_A	404105769	90519996	0	0
GrantKnown_A	404105769	403286744	0	0
IdxKnown_A	404105769	403286744	0	0
IndexIsCorrect_A	404105769	90519996	0	0
NoReadyValidNoGrant_A	404105769	42932083	0	0
Priority_A	404105769	96394853	0	0
ReadyAndValidImplyGrant_A	404105769	90519996	0	0
ReqAndReadyImplyGrant_A	404105769	90519996	0	0
ReqImpliesValid_A	404105769	96394853	0	0
ValidKnown_A	404105769	403286744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	42932083	0	0
T1	2961	46	0	0
T2	57718	0	0	0
T3	1173	0	0	0
T4	122737	872	0	0
T5	90534	0	0	0
T6	346137	40131	0	0
T7	564954	284528	0	0
T11	944	0	0	0
T12	228507	524461	0	0
T17	2779	0	0	0
T18	0	53	0	0
T23	0	12	0	0
T35	0	61	0	0
T36	0	81324	0	0
T40	0	524466	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	96394853	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38682	0	0
T5	90534	18692	0	0
T6	346137	158530	0	0
T7	564954	128933	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	96394853	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38682	0	0
T5	90534	18692	0	0
T6	346137	158530	0	0
T7	564954	128933	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404105769	403286744	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	404105769	90519996	0	0
GntImpliesValid_A	404105769	90519996	0	0
GrantKnown_A	404105769	403286744	0	0
IdxKnown_A	404105769	403286744	0	0
IndexIsCorrect_A	404105769	90519996	0	0
NoReadyValidNoGrant_A	404105769	42932083	0	0
Priority_A	404105769	96394853	0	0
ReadyAndValidImplyGrant_A	404105769	90519996	0	0
ReqAndReadyImplyGrant_A	404105769	90519996	0	0
ReqImpliesValid_A	404105769	96394853	0	0
ValidKnown_A	404105769	403286744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	42932083	0	0
T1	2961	46	0	0
T2	57718	0	0	0
T3	1173	0	0	0
T4	122737	872	0	0
T5	90534	0	0	0
T6	346137	40131	0	0
T7	564954	284528	0	0
T11	944	0	0	0
T12	228507	524461	0	0
T17	2779	0	0	0
T18	0	53	0	0
T23	0	12	0	0
T35	0	61	0	0
T36	0	81324	0	0
T40	0	524466	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	96394853	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38682	0	0
T5	90534	18692	0	0
T6	346137	158530	0	0
T7	564954	128933	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	90519996	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38664	0	0
T5	90534	18692	0	0
T6	346137	133283	0	0
T7	564954	8025	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	96394853	0	0
T1	2961	16	0	0
T2	57718	7269	0	0
T3	1173	0	0	0
T4	122737	38682	0	0
T5	90534	18692	0	0
T6	346137	158530	0	0
T7	564954	128933	0	0
T11	944	0	0	0
T12	228507	413286	0	0
T17	2779	0	0	0
T18	0	23	0	0
T35	0	42160	0	0
T40	0	413433	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404105769	403286744	0	0
T1	2961	2838	0	0
T2	57718	57653	0	0
T3	1173	1076	0	0
T4	122737	122675	0	0
T5	90534	89488	0	0
T6	346137	346040	0	0
T7	564954	564815	0	0
T11	944	858	0	0
T12	228507	228505	0	0
T17	2779	2688	0	0