Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T18,T40 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T18,T40 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5240735 |
0 |
0 |
T1 |
23688 |
36 |
0 |
0 |
T2 |
461744 |
0 |
0 |
0 |
T3 |
9384 |
5 |
0 |
0 |
T4 |
981896 |
457 |
0 |
0 |
T5 |
724272 |
0 |
0 |
0 |
T6 |
2769096 |
46306 |
0 |
0 |
T7 |
4519632 |
17025 |
0 |
0 |
T11 |
7552 |
0 |
0 |
0 |
T12 |
1828056 |
98 |
0 |
0 |
T17 |
22232 |
0 |
0 |
0 |
T18 |
0 |
32 |
0 |
0 |
T23 |
0 |
54 |
0 |
0 |
T32 |
0 |
5685 |
0 |
0 |
T35 |
0 |
467 |
0 |
0 |
T36 |
0 |
21162 |
0 |
0 |
T40 |
0 |
133 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5240726 |
0 |
0 |
T1 |
23688 |
36 |
0 |
0 |
T2 |
461744 |
0 |
0 |
0 |
T3 |
9384 |
5 |
0 |
0 |
T4 |
981896 |
457 |
0 |
0 |
T5 |
724272 |
0 |
0 |
0 |
T6 |
2769096 |
46306 |
0 |
0 |
T7 |
4519632 |
17025 |
0 |
0 |
T11 |
7552 |
0 |
0 |
0 |
T12 |
1828056 |
98 |
0 |
0 |
T17 |
22232 |
0 |
0 |
0 |
T18 |
0 |
32 |
0 |
0 |
T23 |
0 |
54 |
0 |
0 |
T32 |
0 |
5685 |
0 |
0 |
T35 |
0 |
467 |
0 |
0 |
T36 |
0 |
21162 |
0 |
0 |
T40 |
0 |
133 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T44,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T40,T44,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728816 |
0 |
0 |
T1 |
2961 |
6 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
2 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5709 |
0 |
0 |
T7 |
564954 |
2250 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
114 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728815 |
0 |
0 |
T1 |
2961 |
6 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
2 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5709 |
0 |
0 |
T7 |
564954 |
2250 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
114 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T44,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T40,T44,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728683 |
0 |
0 |
T1 |
2961 |
6 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5704 |
0 |
0 |
T7 |
564954 |
2252 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
114 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728683 |
0 |
0 |
T1 |
2961 |
6 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5704 |
0 |
0 |
T7 |
564954 |
2252 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
114 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T40,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T40,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728246 |
0 |
0 |
T1 |
2961 |
7 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5720 |
0 |
0 |
T7 |
564954 |
2243 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
113 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728246 |
0 |
0 |
T1 |
2961 |
7 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5720 |
0 |
0 |
T7 |
564954 |
2243 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T35 |
0 |
113 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T18,T40 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T18,T40 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728148 |
0 |
0 |
T1 |
2961 |
7 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5701 |
0 |
0 |
T7 |
564954 |
2255 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T35 |
0 |
113 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
728147 |
0 |
0 |
T1 |
2961 |
7 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
1 |
0 |
0 |
T4 |
122737 |
66 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5701 |
0 |
0 |
T7 |
564954 |
2255 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
11 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T35 |
0 |
113 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T76,T77,T78 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T76,T77,T78 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581831 |
0 |
0 |
T1 |
2961 |
3 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
49 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5871 |
0 |
0 |
T7 |
564954 |
2007 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
14 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
5275 |
0 |
0 |
T40 |
0 |
16 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581830 |
0 |
0 |
T1 |
2961 |
3 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
49 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5871 |
0 |
0 |
T7 |
564954 |
2007 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
14 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
5275 |
0 |
0 |
T40 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T79,T76,T77 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T79,T76,T77 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581836 |
0 |
0 |
T1 |
2961 |
3 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5862 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
14 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5284 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581834 |
0 |
0 |
T1 |
2961 |
3 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5862 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
14 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5284 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T76,T77,T78 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T76,T77,T78 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581742 |
0 |
0 |
T1 |
2961 |
2 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5870 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
13 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5310 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581739 |
0 |
0 |
T1 |
2961 |
2 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5870 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
13 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5310 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T12,T40,T28 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T76,T77,T78 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T12,T40,T28 |
0 |
0 |
1 |
- |
- |
Covered |
T76,T77,T78 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581433 |
0 |
0 |
T1 |
2961 |
2 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5869 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
13 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T32 |
0 |
5685 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5293 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404105769 |
581432 |
0 |
0 |
T1 |
2961 |
2 |
0 |
0 |
T2 |
57718 |
0 |
0 |
0 |
T3 |
1173 |
0 |
0 |
0 |
T4 |
122737 |
48 |
0 |
0 |
T5 |
90534 |
0 |
0 |
0 |
T6 |
346137 |
5869 |
0 |
0 |
T7 |
564954 |
2006 |
0 |
0 |
T11 |
944 |
0 |
0 |
0 |
T12 |
228507 |
13 |
0 |
0 |
T17 |
2779 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T32 |
0 |
5685 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
5293 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |