Unified Coverage Report :: Module :: flash_ctrl_prog

Module : flash_ctrl_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.17	100.00	97.06			94.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_ctrl_prog	97.17	100.00	97.06			94.44

---

Module Instance : tb.dut.u_flash_ctrl_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.17	100.00	97.06			94.44

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.88	100.00	97.06	100.00		94.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_prog

	Line No.	Total	Covered	Percent
TOTAL		54	54	100.00
ALWAYS	55	3	3	100.00
ALWAYS	90	4	4	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	101	5	5	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	132	26	26	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	193	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
58	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
103	1	1
104	1	1
106	1	1
112	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
144	1	1
146	1	1
148	1	1
150	1	1
152	1	1
153	1	1
154	1	1
155	1	1
157	1	1
158	1	1
160	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
174	1	1
175	1	1
176	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
193	1	1

---

Cond Coverage for Module : flash_ctrl_prog

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T137,T168,T169
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       97
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       103
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T137,T168,T169
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION (start_window != end_window)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (pgm_res_err | op_addr_oob_i)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       148
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T83,T97
1	1	0	Covered	T2,T136,T170
1	1	1	Covered	T1,T2,T4

 LINE       160
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T6,T35

 LINE       164
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T2,T5,T83

 LINE       164
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T83,T97

 LINE       174
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       187
 EXPRESSION (flash_req_o & cnt_hit)
             -----1-----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : flash_ctrl_prog

	Line No.	Total	Covered	Percent
Branches		18	17	94.44
IF	55	2	2	100.00
IF	90	3	3	100.00
IF	101	3	3	100.00
CASE	138	10	9	90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (((~|op_err_q) && (|op_err_d)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((op_start_i && op_done_o))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	case (st_q)
-2-:	144	if (cnt_err_o)
-3-:	148	if (((op_start_i && prog_type_avail) && (!win_err)))
-4-:	152	if (txn_done)
-5-:	157	if (cnt_hit)
-6-:	160	((|op_err_d)) ? 
-7-:	164	if ((op_start_i && ((!prog_type_avail) || win_err)))
-8-:	174	if ((data_rdy_i && cnt_hit))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StNorm	1	-	-	-	-	-	-	Covered	T15,T8,T16
StNorm	0	1	1	1	-	-	-	Covered	T1,T2,T4
StNorm	0	1	1	0	1	-	-	Covered	T4,T6,T35
StNorm	0	1	1	0	0	-	-	Covered	T1,T2,T4
StNorm	0	1	0	-	-	-	-	Covered	T1,T2,T4
StNorm	0	0	-	-	-	1	-	Covered	T2,T5,T83
StNorm	0	0	-	-	-	0	-	Covered	T1,T2,T3
StErr	-	-	-	-	-	-	1	Covered	T2,T4,T5
StErr	-	-	-	-	-	-	0	Covered	T2,T4,T5
default	-	-	-	-	-	-	-	Not Covered