Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alert_senders[4].u_alert_sender	77.78			77.78
tb.dut.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[2].u_alert_sender	100.00			100.00
tb.dut.gen_alert_senders[3].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.gen_alert_senders[4].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78			77.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.66	97.12	94.40	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_ack_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[4].u_alert_sender

	Total	Covered	Percent
Totals	9	7	77.78
Total Bits	18	14	77.78
Total Bits 0->1	9	7	77.78
Total Bits 1->0	9	7	77.78

Ports	9	7	77.78
Port Bits	18	14	77.78
Port Bits 0->1	9	7	77.78
Port Bits 1->0	9	7	77.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Unreachable	Unreachable		Unreachable		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_ack_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Yes	Yes	T128,T137,T15	Yes	T128,T137,T15	INPUT
alert_ack_o	Yes	Yes	T137,T15,T28	Yes	T137,T15,T28	OUTPUT
alert_state_o	Yes	Yes	T128,T137,T15	Yes	T128,T137,T15	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T137,T175	Yes	T17,T137,T175	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T128,T137	Yes	T17,T128,T137	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Yes	Yes	T1,T18,T83	Yes	T1,T18,T83	INPUT
alert_ack_o	Yes	Yes	T1,T18,T83	Yes	T1,T18,T83	OUTPUT
alert_state_o	Yes	Yes	T1,T18,T83	Yes	T1,T18,T83	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T17,T18	Yes	T1,T17,T18	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T17,T18	Yes	T1,T17,T18	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_req_i	Yes	Yes	T15,T16,T42	Yes	T15,T16,T42	INPUT
alert_ack_o	Yes	Yes	T65,T184,T185	Yes	T65,T184,T185	OUTPUT
alert_state_o	Yes	Yes	T15,T16,T42	Yes	T15,T16,T42	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T175,T176	Yes	T17,T175,T176	OUTPUT