Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_mp
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 100.00 98.56 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_mp 99.64 100.00 98.56 100.00 100.00



Module Instance : tb.dut.u_flash_mp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 100.00 98.56 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.69 100.00 98.77 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_hw_sel 100.00 100.00 100.00
u_sw_sel 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_mp
Line No.TotalCoveredPercent
TOTAL7676100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
ALWAYS18500
ALWAYS18522100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21511100.00
ALWAYS2401010100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN27011100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN30111100.00
ALWAYS30766100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN37511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
79 1 1
80 1 1
100 1 1
104 1 1
105 1 1
121 1 1
129 1 1
132 1 1
149 9 9
174 1 1
179 1 1
180 1 1
185 1 1
186 1 1
191 1 1
195 1 1
198 1 1
201 1 1
204 1 1
206 1 1
209 1 1
212 1 1
215 1 1
240 1 1
241 1 1
242 1 1
243 1 1
245 1 1
248 1 1
249 1 1
MISSING_ELSE
MISSING_ELSE
254 1 1
255 1 1
257 1 1
262 1 1
263 1 1
266 1 1
269 1 1
270 1 1
271 1 1
273 1 1
274 1 1
277 1 1
278 1 1
281 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
301 1 1
307 1 1
308 1 1
309 1 1
310 1 1
311 1 1
312 1 1
MISSING_ELSE
316 1 1
317 1 1
318 1 1
319 1 1
324 1 1
325 1 1
326 1 1
375 1 1


Cond Coverage for Module : flash_mp
TotalCoveredPercent
Conditions13913798.56
Logical13913798.56
Non-Logical00
Event00

 LINE       100
 EXPRESSION (if_sel_i == HwSel)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       104
 EXPRESSION (req_part_i == FlashPartData)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       105
 EXPRESSION (req_part_i == FlashPartInfo)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
             --1--   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T4,T7
10CoveredT1,T2,T3
11CoveredT7,T214,T242

 LINE       132
 SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
                 -----------1----------   ------2-----   -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT173,T174
010Unreachable
100CoveredT1,T4,T7

 LINE       154
 EXPRESSION (req_i & ((~hw_sel)))
             --1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       164
 EXPRESSION (req_i & hw_sel)
             --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       174
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       186
 EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
             ---------1---------   --------2-------   -----3-----
-1--2--3-StatusTests
011CoveredT2,T5,T12
101CoveredT1,T2,T3
110CoveredT12,T40,T28
111CoveredT2,T5,T12

 LINE       186
 SUB-EXPRESSION (bank_addr == i[0])
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       204
 EXPRESSION (bk_erase_i & ((|bk_erase_en)))
             -----1----   --------2-------
-1--2-StatusTests
01CoveredT2,T5,T12
10CoveredT106,T107,T113
11CoveredT40,T68,T28

 LINE       215
 EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T4
111CoveredT6,T36,T32

 LINE       215
 SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT40,T68,T28
0010CoveredT12,T40,T83
0100CoveredT1,T2,T4
1000CoveredT1,T4,T12

 LINE       242
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       245
 EXPRESSION 
 Number  Term
      1  (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) && 
      2  (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) && 
      3  (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
                -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT8,T14
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
                --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       273
 EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
             ------1------   -----2----   --------3-------
-1--2--3-StatusTests
011CoveredT40,T68,T28
101CoveredT45,T68,T76
110CoveredT106,T107,T113
111CoveredT78,T107,T84

 LINE       281
 EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T4
110CoveredT1,T2,T3
111CoveredT4,T7,T6

 LINE       281
 SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT78,T107,T84
0010CoveredT12,T47,T40
0100CoveredT1,T4,T11
1000CoveredT1,T2,T3

 LINE       289
 EXPRESSION (req_i & (data_rd_en | info_rd_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT1,T4,T7
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       289
 SUB-EXPRESSION (data_rd_en | info_rd_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T12

 LINE       290
 EXPRESSION (req_i & (data_prog_en | info_prog_en))
             --1--   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       290
 SUB-EXPRESSION (data_prog_en | info_prog_en)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T11
10CoveredT1,T2,T4

 LINE       291
 EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT19,T44,T177
10CoveredT1,T2,T3
11CoveredT12,T47,T40

 LINE       291
 SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T47,T40
10CoveredT12,T40,T83

 LINE       292
 EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT40,T68,T28
10CoveredT1,T2,T3
11CoveredT40,T68,T28

 LINE       292
 SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT40,T68,T28

 LINE       293
 EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T4,T11
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (data_scramble_en | info_scramble_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T12

 LINE       294
 EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
             --1--   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T11
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       294
 SUB-EXPRESSION (data_ecc_en | info_ecc_en)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T12

 LINE       295
 EXPRESSION (req_i & (data_he_en | info_he_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       295
 SUB-EXPRESSION (data_he_en | info_he_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       296
 EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
             --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT40,T68,T28
0010CoveredT12,T47,T40
0100CoveredT1,T2,T4
1000CoveredT1,T2,T3

 LINE       316
 EXPRESSION (rd_done_i | txn_err)
             ----1----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T6
10CoveredT1,T2,T3

 LINE       317
 EXPRESSION (prog_done_i | txn_err)
             -----1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T6
10CoveredT1,T2,T4

 LINE       318
 EXPRESSION (erase_done_i | txn_err)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T6
10CoveredT12,T40,T83

 LINE       324
 EXPRESSION (pg_erase_o | bk_erase_o)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT40,T68,T28
10CoveredT12,T47,T40

 LINE       325
 EXPRESSION (erase_valid & erase_suspend_i)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT84,T159,T160
10CoveredT12,T47,T40
11CoveredT156,T84,T157

 LINE       326
 EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
             ------------------1-----------------   ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T84,T157
10CoveredT84,T159,T160

 LINE       326
 SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
                 -------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T84,T157
11CoveredT84,T159,T160

 LINE       326
 SUB-EXPRESSION (erase_suspend_o & erase_done_o)
                 -------1-------   ------2-----
-1--2-StatusTests
01CoveredT4,T7,T12
10CoveredT156,T84,T157
11CoveredT156,T84,T157

Branch Coverage for Module : flash_mp
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 129 2 2 100.00
TERNARY 174 2 2 100.00
TERNARY 263 2 2 100.00
IF 242 2 2 100.00
IF 307 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 129 (data_part_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 174 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 263 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 242 if ((hw_sel && req_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_ni)) -2-: 309 if (txn_err) -3-: 311 if (no_allowed_txn)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T7,T6
0 0 1 Covered T4,T7,T6
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_mp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BankEraseData_A 404105808 7800498 0 0
BankEraseInfo_A 404105808 9634464 0 0
DataReqToInfo_A 404105808 244663773 0 0
InReqOutReq_A 404105808 270644488 0 0
InfoReqToData_A 404105808 25980715 0 0
NoReqWhenErr_A 400895923 130766 0 0
bkEraseEnOnehot_A 404105808 17434962 0 0
hwInfoRuleOnehot_A 404105808 156067245 0 0
invalidReqOnehot_A 404105808 270513683 0 0
requestTypesOnehot_A 404105808 270513683 0 0


BankEraseData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 7800498 0 0
T19 133555 0 0 0
T23 2329 0 0 0
T28 0 131080 0 0
T36 372521 0 0 0
T40 296367 65540 0 0
T68 0 131080 0 0
T69 0 262160 0 0
T71 3333 0 0 0
T83 210890 0 0 0
T84 0 196899 0 0
T104 1033 0 0 0
T109 1865 0 0 0
T110 1088 0 0 0
T111 1086 0 0 0
T133 0 131080 0 0
T195 0 65540 0 0
T240 0 393240 0 0
T243 0 131080 0 0
T244 0 65540 0 0

BankEraseInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 9634464 0 0
T78 129079 111418 0 0
T84 0 65624 0 0
T86 0 327700 0 0
T87 0 524320 0 0
T88 0 983100 0 0
T93 1496 0 0 0
T94 1295 0 0 0
T95 142463 0 0 0
T96 51541 0 0 0
T97 962716 0 0 0
T98 1047 0 0 0
T99 3825 0 0 0
T100 189227 0 0 0
T101 1217 0 0 0
T107 0 327700 0 0
T113 0 458780 0 0
T114 0 720940 0 0
T116 0 65540 0 0
T117 0 131080 0 0

DataReqToInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 244663773 0 0
T1 2961 169 0 0
T2 57718 15299 0 0
T3 1173 0 0 0
T4 122737 102619 0 0
T5 90534 37502 0 0
T6 346137 269609 0 0
T7 564954 0 0 0
T11 944 0 0 0
T12 228507 931469 0 0
T17 2779 0 0 0
T18 0 68 0 0
T35 0 61457 0 0
T40 0 938429 0 0
T83 0 134617 0 0

InReqOutReq_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 270644488 0 0
T1 2961 714 0 0
T2 57718 15459 0 0
T3 1173 160 0 0
T4 122737 107849 0 0
T5 90534 37662 0 0
T6 346137 289758 0 0
T7 564954 144225 0 0
T11 944 334 0 0
T12 228507 936939 0 0
T17 2779 160 0 0

InfoReqToData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 25980715 0 0
T1 2961 545 0 0
T2 57718 160 0 0
T3 1173 160 0 0
T4 122737 5230 0 0
T5 90534 160 0 0
T6 346137 20149 0 0
T7 564954 144225 0 0
T11 944 334 0 0
T12 228507 54700 0 0
T17 2779 160 0 0

NoReqWhenErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 400895923 130766 0 0
T4 122737 160 0 0
T5 90534 0 0 0
T6 346137 768 0 0
T7 564954 8 0 0
T11 944 0 0 0
T12 228507 0 0 0
T17 2779 0 0 0
T18 1627 0 0 0
T19 0 426 0 0
T32 0 1194 0 0
T35 74749 208 0 0
T36 0 946 0 0
T48 2813 0 0 0
T58 0 228 0 0
T61 0 210 0 0
T70 0 6 0 0

bkEraseEnOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 17434962 0 0
T19 133555 0 0 0
T23 2329 0 0 0
T28 0 131080 0 0
T36 372521 0 0 0
T40 296367 65540 0 0
T68 0 131080 0 0
T69 0 262160 0 0
T71 3333 0 0 0
T78 0 111418 0 0
T83 210890 0 0 0
T84 0 262523 0 0
T104 1033 0 0 0
T107 0 327700 0 0
T109 1865 0 0 0
T110 1088 0 0 0
T111 1086 0 0 0
T133 0 131080 0 0
T195 0 65540 0 0
T240 0 393240 0 0

hwInfoRuleOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 156067245 0 0
T1 2961 320 0 0
T2 57718 160 0 0
T3 1173 160 0 0
T4 122737 160 0 0
T5 90534 160 0 0
T6 346137 160 0 0
T7 564954 1835 0 0
T11 944 160 0 0
T12 228507 936286 0 0
T17 2779 160 0 0

invalidReqOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 270513683 0 0
T1 2961 714 0 0
T2 57718 15459 0 0
T3 1173 160 0 0
T4 122737 107689 0 0
T5 90534 37662 0 0
T6 346137 288990 0 0
T7 564954 144217 0 0
T11 944 334 0 0
T12 228507 936939 0 0
T17 2779 160 0 0

requestTypesOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404105808 270513683 0 0
T1 2961 714 0 0
T2 57718 15459 0 0
T3 1173 160 0 0
T4 122737 107689 0 0
T5 90534 37662 0 0
T6 346137 288990 0 0
T7 564954 144217 0 0
T11 944 334 0 0
T12 228507 936939 0 0
T17 2779 160 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%