Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23358698 1 T1 14 T2 105 T3 34
full_word 7804919 1 T1 1 T2 3 T3 131



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 31163287 1 T1 15 T2 108 T3 165
auto[TlIntgErrCmd] 110 1 T67 9 T197 5 T213 2
auto[TlIntgErrData] 111 1 T67 5 T197 6 T213 8
auto[TlIntgErrBoth] 109 1 T67 6 T197 9 T214 7



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26685679 1 T1 14 T2 100 T3 61
auto[1] 4477938 1 T1 1 T2 8 T3 104



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 22683238 1 T1 13 T2 100 T3 18
auto[TlIntgErrNone] partial auto[1] 675161 1 T1 1 T2 5 T3 16
auto[TlIntgErrNone] full_word auto[0] 4002301 1 T1 1 T3 43 T4 15
auto[TlIntgErrNone] full_word auto[1] 3802587 1 T2 3 T3 88 T4 127
auto[TlIntgErrCmd] partial auto[0] 41 1 T67 3 T197 2 T213 1
auto[TlIntgErrCmd] partial auto[1] 59 1 T67 4 T197 3 T214 1
auto[TlIntgErrCmd] full_word auto[0] 7 1 T67 1 T213 1 T264 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T67 1 T264 1 T269 1
auto[TlIntgErrData] partial auto[0] 46 1 T67 3 T197 1 T213 2
auto[TlIntgErrData] partial auto[1] 54 1 T67 2 T197 5 T213 6
auto[TlIntgErrData] full_word auto[0] 4 1 T264 1 T364 1 T368 1
auto[TlIntgErrData] full_word auto[1] 7 1 T256 1 T264 1 T369 1
auto[TlIntgErrBoth] partial auto[0] 41 1 T67 2 T197 5 T214 2
auto[TlIntgErrBoth] partial auto[1] 58 1 T67 4 T197 3 T214 5
auto[TlIntgErrBoth] full_word auto[0] 1 1 T264 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 9 1 T197 1 T264 2 T369 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 16251 1 T67 19 T197 17 T198 261
full_word 4168333 1 T5 9 T6 11 T8 167



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4184271 1 T5 9 T6 11 T8 167
auto[TlIntgErrCmd] 107 1 T67 11 T197 7 T213 2
auto[TlIntgErrData] 99 1 T67 4 T197 7 T213 3
auto[TlIntgErrBoth] 107 1 T67 5 T197 5 T213 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4164147 1 T5 9 T6 11 T8 167
auto[1] 20437 1 T67 9 T197 10 T198 331



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 926 1 T198 20 T211 62 T224 64
auto[TlIntgErrNone] partial auto[1] 15044 1 T198 241 T211 644 T212 16
auto[TlIntgErrNone] full_word auto[0] 4163091 1 T5 9 T6 11 T8 167
auto[TlIntgErrNone] full_word auto[1] 5210 1 T198 90 T211 234 T212 6
auto[TlIntgErrCmd] partial auto[0] 35 1 T67 5 T197 4 T214 1
auto[TlIntgErrCmd] partial auto[1] 66 1 T67 5 T197 3 T213 2
auto[TlIntgErrCmd] full_word auto[0] 3 1 T67 1 T256 1 T370 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T264 1 T369 1 T365 1
auto[TlIntgErrData] partial auto[0] 49 1 T67 3 T197 3 T213 2
auto[TlIntgErrData] partial auto[1] 34 1 T67 1 T197 2 T213 1
auto[TlIntgErrData] full_word auto[0] 9 1 T197 1 T264 1 T364 1
auto[TlIntgErrData] full_word auto[1] 7 1 T197 1 T214 2 T256 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T67 2 T197 1 T213 3
auto[TlIntgErrBoth] partial auto[1] 66 1 T67 3 T197 4 T213 1
auto[TlIntgErrBoth] full_word auto[0] 3 1 T264 1 T260 1 T371 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T213 1 T369 1 T267 1

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