Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.89 100.00 65.22 85.71 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.55 89.52 65.48 82.56 80.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 87.32 100.00 74.29 75.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 69.33 91.43 57.14 68.75 60.00
u_sram_byte 100.00 100.00
u_sramreqfifo 72.63 94.44 54.84 81.25 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.47 100.00 77.31 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.16 89.08 77.29 100.00 89.41 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 98.30 100.00 91.49 100.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 91.67 100.00 72.22 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.18 100.00 84.17 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.24 92.83 83.76 100.00 94.62 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 80.36 100.00 71.43 50.00 100.00
u_reqfifo 96.53 100.00 86.11 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 97.16 100.00 88.64 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 96.53 100.00 86.11 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
83.89 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42600
CONT_ASSIGN42800
CONT_ASSIGN43500
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 unreachable
428 unreachable
435 unreachable
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
93.47 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL6969100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43511100.00
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 1 1
428 1 1
435 1 1
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
95.18 100.00
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL6969100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43511100.00
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 1 1
428 1 1
435 1 1
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
83.89 65.22
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1157565.22
Logical1157565.22
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT8,T18,T40
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T6
000001Unreachable
000010CoveredT2,T3,T4
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T8
11CoveredT4,T5,T6

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T41
11CoveredT4,T5,T6

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110Not Covered
111CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT4,T5,T6

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT4,T5,T6

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
93.47 77.31
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1199277.31
Logical1199277.31
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T20,T42
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT19,T20,T42
010CoveredT19,T20,T42
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT8,T18,T40
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T7
11CoveredT3,T4,T5

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT8,T9,T41
11CoveredT3,T4,T5

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT17,T43
1CoveredT3,T4,T5

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT17,T43
1CoveredT3,T4,T5

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT3,T4,T5
01Not Covered
10CoveredT14,T44,T45

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT3,T4,T5

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T44,T45
11CoveredT3,T4,T5

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT3,T4,T5
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11CoveredT14,T44,T45

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T7
110Not Covered
111CoveredT3,T4,T5

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T5

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T5
110Not Covered
111CoveredT3,T4,T5

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T4,T7
10Not Covered
11CoveredT3,T4,T5

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
95.18 84.17
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions12010184.17
Logical12010184.17
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT13,T46,T24

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T46,T24
010Unreachable
100CoveredT13,T46,T24

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT2,T5,T6
01CoveredT2,T5,T9
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T9

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T47,T23
01CoveredT9,T23,T37
10CoveredT2,T3,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T9,T47
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT5,T6,T8
000001CoveredT46,T24
000010CoveredT2,T9,T48
000100CoveredT22,T49,T50
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT49,T51,T52
10CoveredT5,T6,T8
11CoveredT5,T6,T8

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T22,T23
11CoveredT5,T6,T8

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11CoveredT5,T6,T8

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT5,T6,T8

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT5,T6,T8

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT5,T6,T8
01CoveredT22,T49,T50
10CoveredT37,T38,T53

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT22,T49,T50
1110Not Covered
1111CoveredT5,T6,T8

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT37,T38,T53
11CoveredT5,T6,T8

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT22,T49,T50
10CoveredT5,T6,T8
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT5,T6,T8
101CoveredT1,T2,T3
110CoveredT22,T49,T50
111CoveredT22,T49,T50

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T8
11Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11CoveredT22,T37,T38

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT22,T54,T55
110Not Covered
111CoveredT5,T6,T8

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T49,T50
10CoveredT5,T6,T8

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT8,T9,T10
110CoveredT22,T49,T50
111CoveredT5,T6,T8

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T8
11Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T8
1Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T6,T8

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T6,T8
10Not Covered
11CoveredT5,T6,T8

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T49,T50
11CoveredT5,T6,T8

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 344 2 2 100.00
TERNARY 467 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00
IF 445 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T19,T20
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T22,T11,T49
1 0 1 Covered T3,T4,T5
1 0 0 Covered T4,T5,T6
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T5
1 0 Covered T4,T5,T6
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 445 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1207012338 1204675860 0 0
DataIntgOptions_A 3087 3087 0 0
ReqOutKnown_A 1207012338 1204675860 0 0
SramDwHasByteGranularity_A 3087 3087 0 0
SramDwIsMultipleOfTlulWidth_A 3087 3087 0 0
TlOutKnownIfFifoKnown_A 1207012338 1204675860 0 0
TlOutValidKnown_A 1207012338 1204675860 0 0
WdataOutKnown_A 1207012338 1204675860 0 0
WeOutKnown_A 1207012338 1204675860 0 0
WmaskOutKnown_A 1207012338 1204675860 0 0
adapterNoReadOrWrite 3087 3087 0 0
rvalidHighReqFifoEmpty 1207012338 7519103 0 0
rvalidHighWhenRspFifoFull 1206031962 7512644 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3087 3087 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T14 3 3 0 0
T21 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3087 3087 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T14 3 3 0 0
T21 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3087 3087 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T14 3 3 0 0
T21 3 3 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 1204675860 0 0
T1 3945 3681 0 0
T2 10080 8319 0 0
T3 8076 7806 0 0
T4 10266 10014 0 0
T5 7452 7086 0 0
T6 8622 8193 0 0
T7 351585 351564 0 0
T8 215493 215208 0 0
T14 2514 2343 0 0
T21 5226 4833 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 3087 3087 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T14 3 3 0 0
T21 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1207012338 7519103 0 0
T3 2692 40 0 0
T4 3422 12 0 0
T5 4968 95 0 0
T6 5748 89 0 0
T7 234390 9083 0 0
T8 143662 191 0 0
T9 2146 35 0 0
T10 0 40867 0 0
T14 1676 3 0 0
T21 3484 0 0 0
T22 0 301 0 0
T25 2081 72 0 0
T35 0 7 0 0
T41 64459 42 0 0
T56 1642 33 0 0
T57 0 16 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1206031962 7512644 0 0
T3 2692 40 0 0
T4 3422 12 0 0
T5 4968 95 0 0
T6 5748 89 0 0
T7 234390 9083 0 0
T8 143662 191 0 0
T9 2146 35 0 0
T10 0 40867 0 0
T14 1676 3 0 0
T21 3484 0 0 0
T22 0 301 0 0
T25 2081 72 0 0
T35 0 7 0 0
T41 64459 42 0 0
T56 1642 33 0 0
T57 0 16 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42600
CONT_ASSIGN42800
CONT_ASSIGN43500
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 unreachable
428 unreachable
435 unreachable
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1157565.22
Logical1157565.22
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT8,T18,T40
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T6
000001Unreachable
000010CoveredT2,T3,T4
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T8
11CoveredT4,T5,T6

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T41
11CoveredT4,T5,T6

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110Not Covered
111CoveredT1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT4,T5,T6

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT4,T5,T6

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 28 24 85.71
TERNARY 108 2 2 100.00
TERNARY 293 2 1 50.00
TERNARY 299 3 1 33.33
TERNARY 344 2 2 100.00
TERNARY 467 2 1 50.00
IF 94 2 2 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00
IF 445 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T11,T16,T17
1 0 1 Covered T11,T16,T17
1 0 0 Covered T4,T5,T6
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T11,T16,T17
1 0 Covered T4,T5,T6
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 445 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T11,T16,T17
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 402337446 401558620 0 0
DataIntgOptions_A 1029 1029 0 0
ReqOutKnown_A 402337446 401558620 0 0
SramDwHasByteGranularity_A 1029 1029 0 0
SramDwIsMultipleOfTlulWidth_A 1029 1029 0 0
TlOutKnownIfFifoKnown_A 402337446 401558620 0 0
TlOutValidKnown_A 402337446 401558620 0 0
WdataOutKnown_A 402337446 401558620 0 0
WeOutKnown_A 402337446 401558620 0 0
WmaskOutKnown_A 402337446 401558620 0 0
adapterNoReadOrWrite 1029 1029 0 0
rvalidHighReqFifoEmpty 402337446 0 0 0
rvalidHighWhenRspFifoFull 402337446 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL6969100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43511100.00
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 1 1
428 1 1
435 1 1
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1199277.31
Logical1199277.31
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T20,T42
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT19,T20,T42
010CoveredT19,T20,T42
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT8,T18,T40
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T7
11CoveredT3,T4,T5

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT8,T9,T41
11CoveredT3,T4,T5

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT17,T43
1CoveredT3,T4,T5

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT17,T43
1CoveredT3,T4,T5

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT3,T4,T5
01Not Covered
10CoveredT14,T44,T45

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT3,T4,T5

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T44,T45
11CoveredT3,T4,T5

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT3,T4,T5
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11CoveredT14,T44,T45

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T7
110Not Covered
111CoveredT3,T4,T5

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T5

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T5
110Not Covered
111CoveredT3,T4,T5

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T4,T7
10Not Covered
11CoveredT3,T4,T5

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 344 2 2 100.00
TERNARY 467 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00
IF 445 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T19,T20,T42
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T17,T43
1 0 1 Covered T3,T4,T5
1 0 0 Covered T17,T43
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T5
1 0 Covered T17,T43
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 445 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 402337446 401558620 0 0
DataIntgOptions_A 1029 1029 0 0
ReqOutKnown_A 402337446 401558620 0 0
SramDwHasByteGranularity_A 1029 1029 0 0
SramDwIsMultipleOfTlulWidth_A 1029 1029 0 0
TlOutKnownIfFifoKnown_A 402337446 401558620 0 0
TlOutValidKnown_A 402337446 401558620 0 0
WdataOutKnown_A 402337446 401558620 0 0
WeOutKnown_A 402337446 401558620 0 0
WmaskOutKnown_A 402337446 401558620 0 0
adapterNoReadOrWrite 1029 1029 0 0
rvalidHighReqFifoEmpty 402337446 3260969 0 0
rvalidHighWhenRspFifoFull 401357070 3254510 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 3260969 0 0
T3 2692 40 0 0
T4 3422 12 0 0
T5 2484 86 0 0
T6 2874 78 0 0
T7 117195 9083 0 0
T8 71831 24 0 0
T9 1073 25 0 0
T14 838 3 0 0
T21 1742 0 0 0
T25 0 64 0 0
T41 0 42 0 0
T56 821 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 401357070 3254510 0 0
T3 2692 40 0 0
T4 3422 12 0 0
T5 2484 86 0 0
T6 2874 78 0 0
T7 117195 9083 0 0
T8 71831 24 0 0
T9 1073 25 0 0
T14 838 3 0 0
T21 1742 0 0 0
T25 0 64 0 0
T41 0 42 0 0
T56 821 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL6969100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43511100.00
ALWAYS44133100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
397 1 1
398 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 1 1
428 1 1
435 1 1
441 1 1
445 1 1
447 1 1
MISSING_ELSE
462 1 1
467 1 1
472 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions12010184.17
Logical12010184.17
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT13,T46,T24

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T46,T24
010Unreachable
100CoveredT13,T46,T24

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT2,T5,T6
01CoveredT2,T5,T9
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T9

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T47,T23
01CoveredT9,T23,T37
10CoveredT2,T3,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T9,T47
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT5,T6,T8
000001CoveredT46,T24
000010CoveredT2,T9,T48
000100CoveredT22,T49,T50
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT49,T51,T52
10CoveredT5,T6,T8
11CoveredT5,T6,T8

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T22,T23
11CoveredT5,T6,T8

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11CoveredT5,T6,T8

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT5,T6,T8

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11,T16,T17
1CoveredT5,T6,T8

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT5,T6,T8
01CoveredT22,T49,T50
10CoveredT37,T38,T53

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT22,T49,T50
1110Not Covered
1111CoveredT5,T6,T8

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT37,T38,T53
11CoveredT5,T6,T8

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT22,T49,T50
10CoveredT5,T6,T8
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT5,T6,T8
101CoveredT1,T2,T3
110CoveredT22,T49,T50
111CoveredT22,T49,T50

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T8
11Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11CoveredT22,T37,T38

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT22,T54,T55
110Not Covered
111CoveredT5,T6,T8

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T49,T50
10CoveredT5,T6,T8

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT8,T9,T10
110CoveredT22,T49,T50
111CoveredT5,T6,T8

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T8
11Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T8
1Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T8
11Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T6,T8

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T6,T8
10Not Covered
11CoveredT5,T6,T8

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T49,T50
11CoveredT5,T6,T8

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T8

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 344 2 2 100.00
TERNARY 467 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00
IF 445 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T6


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T5,T6,T8
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T13,T46
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T22,T11,T49
1 0 1 Covered T5,T6,T8
1 0 0 Covered T11,T16,T17
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T5,T6,T8
1 0 Covered T11,T16,T17
0 - Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 445 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T5,T6,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 402337446 401558620 0 0
DataIntgOptions_A 1029 1029 0 0
ReqOutKnown_A 402337446 401558620 0 0
SramDwHasByteGranularity_A 1029 1029 0 0
SramDwIsMultipleOfTlulWidth_A 1029 1029 0 0
TlOutKnownIfFifoKnown_A 402337446 401558620 0 0
TlOutValidKnown_A 402337446 401558620 0 0
WdataOutKnown_A 402337446 401558620 0 0
WeOutKnown_A 402337446 401558620 0 0
WmaskOutKnown_A 402337446 401558620 0 0
adapterNoReadOrWrite 1029 1029 0 0
rvalidHighReqFifoEmpty 402337446 4258134 0 0
rvalidHighWhenRspFifoFull 402337446 4258134 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 401558620 0 0
T1 1315 1227 0 0
T2 3360 2773 0 0
T3 2692 2602 0 0
T4 3422 3338 0 0
T5 2484 2362 0 0
T6 2874 2731 0 0
T7 117195 117188 0 0
T8 71831 71736 0 0
T14 838 781 0 0
T21 1742 1611 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 4258134 0 0
T5 2484 9 0 0
T6 2874 11 0 0
T7 117195 0 0 0
T8 71831 167 0 0
T9 1073 10 0 0
T10 0 40867 0 0
T14 838 0 0 0
T21 1742 0 0 0
T22 0 301 0 0
T25 2081 8 0 0
T35 0 7 0 0
T41 64459 0 0 0
T56 821 33 0 0
T57 0 16 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 402337446 4258134 0 0
T5 2484 9 0 0
T6 2874 11 0 0
T7 117195 0 0 0
T8 71831 167 0 0
T9 1073 10 0 0
T10 0 40867 0 0
T14 838 0 0 0
T21 1742 0 0 0
T22 0 301 0 0
T25 2081 8 0 0
T35 0 7 0 0
T41 64459 0 0 0
T56 821 33 0 0
T57 0 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%