Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.76 95.76

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if.u_page_cnt 78.79 78.79
tb.dut.u_flash_hw_if.u_seed_cnt 100.00 100.00
tb.dut.u_flash_hw_if.u_addr_cnt 100.00 100.00
tb.dut.u_flash_hw_if.u_word_cnt 100.00 100.00
tb.dut.u_flash_hw_if.u_wipe_idx_cnt 100.00 100.00
tb.dut.u_flash_ctrl_prog.u_cnt 100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_flash_ctrl_rd.u_cnt 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_page_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.79 78.79


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.79 78.79


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.54 100.00 91.67 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_seed_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.54 100.00 91.67 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.54 100.00 91.67 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_word_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.54 100.00 91.67 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_wipe_idx_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.54 100.00 91.67 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_ctrl_prog.u_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 97.06 94.44 u_flash_ctrl_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_ctrl_rd.u_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 100.00 96.97 100.00 95.24 u_flash_ctrl_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.68 100.00 90.57 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.10 100.00 91.30 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.74 100.00 85.85 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=10,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_flash_hw_if.u_word_cnt

TotalCoveredPercent
Totals 8 8 100.00
Total Bits 52 52 100.00
Total Bits 0->1 26 26 100.00
Total Bits 1->0 26 26 100.00

Ports 8 8 100.00
Port Bits 52 52 100.00
Port Bits 0->1 26 26 100.00
Port Bits 1->0 26 26 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_i Yes Yes T18,T113,T111 Yes T18,T113,T111 INPUT
set_cnt_i[9:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[9:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[9:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=12,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_flash_ctrl_prog.u_cnt

SCORETOGGLE
100.00 100.00
tb.dut.u_flash_ctrl_rd.u_cnt

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 58 58 100.00
Total Bits 0->1 29 29 100.00
Total Bits 1->0 29 29 100.00

Ports 7 7 100.00
Port Bits 58 58 100.00
Port Bits 0->1 29 29 100.00
Port Bits 1->0 29 29 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_flash_hw_if.u_seed_cnt

SCORETOGGLE
100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

TotalCoveredPercent
Totals 9 9 100.00
Total Bits 22 22 100.00
Total Bits 0->1 11 11 100.00
Total Bits 1->0 11 11 100.00

Ports 9 9 100.00
Port Bits 22 22 100.00
Port Bits 0->1 11 11 100.00
Port Bits 1->0 11 11 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_flash_hw_if.u_addr_cnt

SCORETOGGLE
100.00 100.00
tb.dut.u_flash_hw_if.u_wipe_idx_cnt

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 22 22 100.00
Total Bits 0->1 11 11 100.00
Total Bits 1->0 11 11 100.00

Ports 7 7 100.00
Port Bits 22 22 100.00
Port Bits 0->1 11 11 100.00
Port Bits 1->0 11 11 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=9,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
78.79 78.79
tb.dut.u_flash_hw_if.u_page_cnt

TotalCoveredPercent
Totals 9 8 88.89
Total Bits 66 52 78.79
Total Bits 0->1 33 26 78.79
Total Bits 1->0 33 26 78.79

Ports 9 8 88.89
Port Bits 66 52 78.79
Port Bits 0->1 33 26 78.79
Port Bits 1->0 33 26 78.79

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_i Yes Yes T18,T48,T47 Yes T18,T48,T47 INPUT
set_cnt_i[1:0] Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_cnt_i[8:2] No No No INPUT
incr_en_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[8:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes T18,T48,T47 Yes T18,T48,T47 OUTPUT
cnt_after_commit_o[8:0] Yes Yes T18,T48,T47 Yes T18,T48,T47 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
TotalCoveredPercent
Totals 9 8 88.89
Total Bits 66 52 78.79
Total Bits 0->1 33 26 78.79
Total Bits 1->0 33 26 78.79

Ports 9 8 88.89
Port Bits 66 52 78.79
Port Bits 0->1 33 26 78.79
Port Bits 1->0 33 26 78.79

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_i Yes Yes T18,T48,T47 Yes T18,T48,T47 INPUT
set_cnt_i[1:0] Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_cnt_i[8:2] No No No INPUT
incr_en_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[8:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[8:0] Yes Yes T18,T48,T47 Yes T18,T48,T47 OUTPUT
cnt_after_commit_o[8:0] Yes Yes T18,T48,T47 Yes T18,T48,T47 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_seed_cnt
TotalCoveredPercent
Totals 6 6 100.00
Total Bits 16 16 100.00
Total Bits 0->1 8 8 100.00
Total Bits 1->0 8 8 100.00

Ports 6 6 100.00
Port Bits 16 16 100.00
Port Bits 0->1 8 8 100.00
Port Bits 1->0 8 8 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 22 22 100.00
Total Bits 0->1 11 11 100.00
Total Bits 1->0 11 11 100.00

Ports 7 7 100.00
Port Bits 22 22 100.00
Port Bits 0->1 11 11 100.00
Port Bits 1->0 11 11 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 52 52 100.00
Total Bits 0->1 26 26 100.00
Total Bits 1->0 26 26 100.00

Ports 8 8 100.00
Port Bits 52 52 100.00
Port Bits 0->1 26 26 100.00
Port Bits 1->0 26 26 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
set_i Yes Yes T18,T113,T111 Yes T18,T113,T111 INPUT
set_cnt_i[9:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[9:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[9:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_wipe_idx_cnt
TotalCoveredPercent
Totals 6 6 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 6 6 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T18,T111,T112 Yes T18,T111,T112 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T18,T111,T112 Yes T18,T111,T112 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T18,T111,T112 Yes T18,T111,T112 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_ctrl_prog.u_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 58 58 100.00
Total Bits 0->1 29 29 100.00
Total Bits 1->0 29 29 100.00

Ports 7 7 100.00
Port Bits 58 58 100.00
Port Bits 0->1 29 29 100.00
Port Bits 1->0 29 29 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[11:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cnt_after_commit_o[11:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
incr_en_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
incr_en_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_ctrl_rd.u_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 58 58 100.00
Total Bits 0->1 29 29 100.00
Total Bits 1->0 29 29 100.00

Ports 7 7 100.00
Port Bits 58 58 100.00
Port Bits 0->1 29 29 100.00
Port Bits 1->0 29 29 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[11:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[11:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_outstanding_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T20,T42,T58 Yes T20,T42,T58 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_outstanding_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
decr_en_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
incr_en_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
incr_en_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
incr_en_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 8 8 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
incr_en_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
err_o Yes Yes T19,T20,T42 Yes T19,T20,T42 OUTPUT

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