Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27886572	1		T1	32970		T2	33582		T3	412
full_word	7728430	1		T1	9394		T2	9443		T3	147

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35614662	1		T1	42364		T2	43025		T3	559
auto[TlIntgErrCmd]	114	1		T66	8		T67	5		T233	6
auto[TlIntgErrData]	116	1		T66	8		T67	4		T233	8
auto[TlIntgErrBoth]	110	1		T66	4		T67	11		T233	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31116195	1		T1	34602		T2	35225		T3	468
auto[1]	4498807	1		T1	7762		T2	7800		T3	91

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27198183	1		T1	32020		T2	32583		T3	394
auto[TlIntgErrNone]	partial	auto[1]	688090	1		T1	950		T2	999		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	3917850	1		T1	2582		T2	2642		T3	74
auto[TlIntgErrNone]	full_word	auto[1]	3810539	1		T1	6812		T2	6801		T3	73
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T66	4		T67	2		T233	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T66	3		T67	3		T233	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T66	1		T340	1		T261	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T233	1		T261	1		T262	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T66	4		T67	2		T233	2
auto[TlIntgErrData]	partial	auto[1]	47	1		T66	4		T67	2		T233	4
auto[TlIntgErrData]	full_word	auto[0]	7	1		T233	1		T340	1		T344	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T233	1		T340	1		T261	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1		T66	1		T67	5		T233	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T66	2		T67	5		T233	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T67	1		T233	1		T261	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T66	1		T340	2		T261	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19066	1		T212	930		T213	740		T66	20
full_word	4064521	1		T3	11		T4	10		T18	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4083274	1		T3	11		T4	10		T18	10
auto[TlIntgErrCmd]	103	1		T66	4		T67	3		T233	4
auto[TlIntgErrData]	94	1		T66	8		T67	8		T233	5
auto[TlIntgErrBoth]	116	1		T66	8		T67	9		T233	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4058767	1		T3	11		T4	10		T18	10
auto[1]	24820	1		T212	1575		T213	934		T66	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1303	1		T212	64		T213	52		T222	20
auto[TlIntgErrNone]	partial	auto[1]	17472	1		T212	866		T213	688		T222	823
auto[TlIntgErrNone]	full_word	auto[0]	4057337	1		T3	11		T4	10		T18	10
auto[TlIntgErrNone]	full_word	auto[1]	7162	1		T212	709		T213	246		T222	145
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T66	1		T67	1		T233	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T66	3		T67	1		T233	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T67	1		T347	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T261	1		T344	1		T342	2
auto[TlIntgErrData]	partial	auto[0]	44	1		T66	5		T67	3		T339	3
auto[TlIntgErrData]	partial	auto[1]	41	1		T66	3		T67	3		T233	5
auto[TlIntgErrData]	full_word	auto[0]	4	1		T67	1		T340	1		T262	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T67	1		T261	1		T343	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T66	3		T67	3		T233	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1		T66	5		T67	6		T233	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T344	1		T346	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T233	1		T344	1		T345	1