Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1493426540	1489835256	0	0
CheckNGreaterZero_A	4076	4076	0	0
GntImpliesReady_A	1493426540	409023821	0	0
GntImpliesValid_A	1493426540	409023821	0	0
GrantKnown_A	1493426540	1489835256	0	0
IdxKnown_A	1493426540	1489835256	0	0
IndexIsCorrect_A	1493426540	409023821	0	0
NoReadyValidNoGrant_A	1493426540	175155196	0	0
Priority_A	1493426540	433021081	0	0
ReadyAndValidImplyGrant_A	1493426540	409023821	0	0
ReqAndReadyImplyGrant_A	1493426540	409023821	0	0
ReqImpliesValid_A	1493426540	433021081	0	0
ValidKnown_A	1493426540	1489835256	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	1489835256	0	0
T1	383772	383392	0	0
T2	387140	386740	0	0
T3	7580	6944	0	0
T4	5576	5200	0	0
T5	17068	16792	0	0
T9	5288	4996	0	0
T12	16284	13800	0	0
T17	5808	5436	0	0
T18	8856	8252	0	0
T19	646948	646676	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4076	4076	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	409023821	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	596	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	409023821	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	596	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	1489835256	0	0
T1	383772	383392	0	0
T2	387140	386740	0	0
T3	7580	6944	0	0
T4	5576	5200	0	0
T5	17068	16792	0	0
T9	5288	4996	0	0
T12	16284	13800	0	0
T17	5808	5436	0	0
T18	8856	8252	0	0
T19	646948	646676	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	1489835256	0	0
T1	383772	383392	0	0
T2	387140	386740	0	0
T3	7580	6944	0	0
T4	5576	5200	0	0
T5	17068	16792	0	0
T9	5288	4996	0	0
T12	16284	13800	0	0
T17	5808	5436	0	0
T18	8856	8252	0	0
T19	646948	646676	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	409023821	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	596	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	175155196	0	0
T1	383772	7236	0	0
T2	387140	7444	0	0
T3	7580	918	0	0
T4	5576	286	0	0
T5	17068	256	0	0
T6	0	208	0	0
T7	0	583178	0	0
T8	0	580	0	0
T9	5288	256	0	0
T12	16284	1376	0	0
T17	5808	256	0	0
T18	8856	940	0	0
T19	646948	7408	0	0
T39	0	42	0	0
T58	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	433021081	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	628	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	409023821	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	596	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	409023821	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	596	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	433021081	0	0
T1	383772	120358	0	0
T2	387140	122548	0	0
T3	7580	624	0	0
T4	5576	84	0	0
T5	17068	2646	0	0
T6	0	628	0	0
T9	5288	520	0	0
T12	16284	370	0	0
T17	5808	64	0	0
T18	8856	526	0	0
T19	646948	109530	0	0
T39	0	28	0	0
T58	0	255794	0	0
T59	0	123036	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1493426540	1489835256	0	0
T1	383772	383392	0	0
T2	387140	386740	0	0
T3	7580	6944	0	0
T4	5576	5200	0	0
T5	17068	16792	0	0
T9	5288	4996	0	0
T12	16284	13800	0	0
T17	5808	5436	0	0
T18	8856	8252	0	0
T19	646948	646676	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373356635	372458814	0	0
CheckNGreaterZero_A	1019	1019	0	0
GntImpliesReady_A	373356635	112159300	0	0
GntImpliesValid_A	373356635	112159300	0	0
GrantKnown_A	373356635	372458814	0	0
IdxKnown_A	373356635	372458814	0	0
IndexIsCorrect_A	373356635	112159300	0	0
NoReadyValidNoGrant_A	373356635	45841872	0	0
Priority_A	373356635	118200485	0	0
ReadyAndValidImplyGrant_A	373356635	112159300	0	0
ReqAndReadyImplyGrant_A	373356635	112159300	0	0
ReqImpliesValid_A	373356635	118200485	0	0
ValidKnown_A	373356635	372458814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159300	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159300	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159300	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	45841872	0	0
T1	95943	1602	0	0
T2	96785	1880	0	0
T3	1895	388	0	0
T4	1394	143	0	0
T5	4267	128	0	0
T9	1322	128	0	0
T12	4071	688	0	0
T17	1452	128	0	0
T18	2214	365	0	0
T19	161737	1730	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	118200485	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159300	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159300	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	118200485	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373356635	372458814	0	0
CheckNGreaterZero_A	1019	1019	0	0
GntImpliesReady_A	373356635	112159305	0	0
GntImpliesValid_A	373356635	112159305	0	0
GrantKnown_A	373356635	372458814	0	0
IdxKnown_A	373356635	372458814	0	0
IndexIsCorrect_A	373356635	112159305	0	0
NoReadyValidNoGrant_A	373356635	45841866	0	0
Priority_A	373356635	118200496	0	0
ReadyAndValidImplyGrant_A	373356635	112159305	0	0
ReqAndReadyImplyGrant_A	373356635	112159305	0	0
ReqImpliesValid_A	373356635	118200496	0	0
ValidKnown_A	373356635	372458814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159305	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159305	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159305	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	45841866	0	0
T1	95943	1602	0	0
T2	96785	1880	0	0
T3	1895	388	0	0
T4	1394	143	0	0
T5	4267	128	0	0
T9	1322	128	0	0
T12	4071	688	0	0
T17	1452	128	0	0
T18	2214	365	0	0
T19	161737	1730	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	118200496	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159305	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	112159305	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	118200496	0	0
T1	95943	25851	0	0
T2	96785	29953	0	0
T3	1895	115	0	0
T4	1394	42	0	0
T5	4267	554	0	0
T9	1322	260	0	0
T12	4071	185	0	0
T17	1452	32	0	0
T18	2214	224	0	0
T19	161737	24487	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T18,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T18,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T18,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T18,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373356635	372458814	0	0
CheckNGreaterZero_A	1019	1019	0	0
GntImpliesReady_A	373356635	92352608	0	0
GntImpliesValid_A	373356635	92352608	0	0
GrantKnown_A	373356635	372458814	0	0
IdxKnown_A	373356635	372458814	0	0
IndexIsCorrect_A	373356635	92352608	0	0
NoReadyValidNoGrant_A	373356635	41735729	0	0
Priority_A	373356635	98310050	0	0
ReadyAndValidImplyGrant_A	373356635	92352608	0	0
ReqAndReadyImplyGrant_A	373356635	92352608	0	0
ReqImpliesValid_A	373356635	98310050	0	0
ValidKnown_A	373356635	372458814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	41735729	0	0
T1	95943	2016	0	0
T2	96785	1842	0	0
T3	1895	71	0	0
T4	1394	0	0	0
T5	4267	0	0	0
T6	0	104	0	0
T7	0	291589	0	0
T8	0	290	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	105	0	0
T19	161737	1974	0	0
T39	0	21	0	0
T58	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	98310050	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	314	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	98310050	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	314	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T18,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T18,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T18,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T18,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373356635	372458814	0	0
CheckNGreaterZero_A	1019	1019	0	0
GntImpliesReady_A	373356635	92352608	0	0
GntImpliesValid_A	373356635	92352608	0	0
GrantKnown_A	373356635	372458814	0	0
IdxKnown_A	373356635	372458814	0	0
IndexIsCorrect_A	373356635	92352608	0	0
NoReadyValidNoGrant_A	373356635	41735729	0	0
Priority_A	373356635	98310050	0	0
ReadyAndValidImplyGrant_A	373356635	92352608	0	0
ReqAndReadyImplyGrant_A	373356635	92352608	0	0
ReqImpliesValid_A	373356635	98310050	0	0
ValidKnown_A	373356635	372458814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	41735729	0	0
T1	95943	2016	0	0
T2	96785	1842	0	0
T3	1895	71	0	0
T4	1394	0	0	0
T5	4267	0	0	0
T6	0	104	0	0
T7	0	291589	0	0
T8	0	290	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	105	0	0
T19	161737	1974	0	0
T39	0	21	0	0
T58	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	98310050	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	314	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	92352608	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	298	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	98310050	0	0
T1	95943	34328	0	0
T2	96785	31321	0	0
T3	1895	197	0	0
T4	1394	0	0	0
T5	4267	769	0	0
T6	0	314	0	0
T9	1322	0	0	0
T12	4071	0	0	0
T17	1452	0	0	0
T18	2214	39	0	0
T19	161737	30278	0	0
T39	0	14	0	0
T58	0	127897	0	0
T59	0	61518	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373356635	372458814	0	0
T1	95943	95848	0	0
T2	96785	96685	0	0
T3	1895	1736	0	0
T4	1394	1300	0	0
T5	4267	4198	0	0
T9	1322	1249	0	0
T12	4071	3450	0	0
T17	1452	1359	0	0
T18	2214	2063	0	0
T19	161737	161669	0	0