Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	97.12	95.20	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	376075937	4739	0	0
addr_rd_A	376075937	2520	0	0
bank0_info0_page_cfg_0_rd_A	376075937	2390	0	0
bank0_info0_page_cfg_1_rd_A	376075937	3457	0	0
bank0_info0_page_cfg_2_rd_A	376075937	2411	0	0
bank0_info0_page_cfg_3_rd_A	376075937	2808	0	0
bank0_info0_page_cfg_4_rd_A	376075937	3263	0	0
bank0_info0_page_cfg_5_rd_A	376075937	3242	0	0
bank0_info0_page_cfg_6_rd_A	376075937	2645	0	0
bank0_info0_page_cfg_7_rd_A	376075937	2181	0	0
bank0_info0_page_cfg_8_rd_A	376075937	2283	0	0
bank0_info0_page_cfg_9_rd_A	376075937	2961	0	0
bank0_info0_regwen_0_rd_A	376075937	1390	0	0
bank0_info0_regwen_1_rd_A	376075937	2434	0	0
bank0_info0_regwen_2_rd_A	376075937	1941	0	0
bank0_info0_regwen_3_rd_A	376075937	2663	0	0
bank0_info0_regwen_4_rd_A	376075937	2240	0	0
bank0_info0_regwen_5_rd_A	376075937	2405	0	0
bank0_info0_regwen_6_rd_A	376075937	2321	0	0
bank0_info0_regwen_7_rd_A	376075937	1424	0	0
bank0_info0_regwen_8_rd_A	376075937	2361	0	0
bank0_info0_regwen_9_rd_A	376075937	2201	0	0
bank0_info1_page_cfg_rd_A	376075937	2938	0	0
bank0_info1_regwen_rd_A	376075937	1438	0	0
bank0_info2_page_cfg_0_rd_A	376075937	3373	0	0
bank0_info2_page_cfg_1_rd_A	376075937	3544	0	0
bank0_info2_regwen_0_rd_A	376075937	1860	0	0
bank0_info2_regwen_1_rd_A	376075937	1998	0	0
bank1_info0_page_cfg_0_rd_A	376075937	3296	0	0
bank1_info0_page_cfg_1_rd_A	376075937	3490	0	0
bank1_info0_page_cfg_2_rd_A	376075937	2771	0	0
bank1_info0_page_cfg_3_rd_A	376075937	2717	0	0
bank1_info0_page_cfg_4_rd_A	376075937	3195	0	0
bank1_info0_page_cfg_5_rd_A	376075937	2820	0	0
bank1_info0_page_cfg_6_rd_A	376075937	3161	0	0
bank1_info0_page_cfg_7_rd_A	376075937	3471	0	0
bank1_info0_page_cfg_8_rd_A	376075937	3539	0	0
bank1_info0_page_cfg_9_rd_A	376075937	3104	0	0
bank1_info0_regwen_0_rd_A	376075937	1334	0	0
bank1_info0_regwen_1_rd_A	376075937	1823	0	0
bank1_info0_regwen_2_rd_A	376075937	2104	0	0
bank1_info0_regwen_3_rd_A	376075937	2398	0	0
bank1_info0_regwen_4_rd_A	376075937	1967	0	0
bank1_info0_regwen_5_rd_A	376075937	2371	0	0
bank1_info0_regwen_6_rd_A	376075937	1924	0	0
bank1_info0_regwen_7_rd_A	376075937	2379	0	0
bank1_info0_regwen_8_rd_A	376075937	1406	0	0
bank1_info0_regwen_9_rd_A	376075937	1801	0	0
bank1_info1_page_cfg_rd_A	376075937	3165	0	0
bank1_info1_regwen_rd_A	376075937	2509	0	0
bank1_info2_page_cfg_0_rd_A	376075937	3657	0	0
bank1_info2_page_cfg_1_rd_A	376075937	3330	0	0
bank1_info2_regwen_0_rd_A	376075937	1993	0	0
bank1_info2_regwen_1_rd_A	376075937	2495	0	0
bank_cfg_regwen_rd_A	376075937	2497	0	0
default_region_rd_A	376075937	2195	0	0
exec_rd_A	376075937	2459	0	0
fifo_lvl_rd_A	376075937	2713	0	0
fifo_rst_rd_A	376075937	1521	0	0
hw_info_cfg_override_rd_A	376075937	2667	0	0
intr_enable_rd_A	376075937	2651	0	0
mp_region_0_rd_A	376075937	1937	0	0
mp_region_1_rd_A	376075937	2595	0	0
mp_region_2_rd_A	376075937	2120	0	0
mp_region_3_rd_A	376075937	2617	0	0
mp_region_4_rd_A	376075937	2546	0	0
mp_region_5_rd_A	376075937	2324	0	0
mp_region_6_rd_A	376075937	2455	0	0
mp_region_7_rd_A	376075937	2037	0	0
mp_region_cfg_0_rd_A	376075937	3376	0	0
mp_region_cfg_1_rd_A	376075937	3463	0	0
mp_region_cfg_2_rd_A	376075937	3516	0	0
mp_region_cfg_3_rd_A	376075937	2753	0	0
mp_region_cfg_4_rd_A	376075937	2515	0	0
mp_region_cfg_5_rd_A	376075937	3381	0	0
mp_region_cfg_6_rd_A	376075937	3280	0	0
mp_region_cfg_7_rd_A	376075937	2814	0	0
phy_alert_cfg_rd_A	376075937	1171	0	0
region_cfg_regwen_0_rd_A	376075937	2438	0	0
region_cfg_regwen_1_rd_A	376075937	2409	0	0
region_cfg_regwen_2_rd_A	376075937	2438	0	0
region_cfg_regwen_3_rd_A	376075937	1937	0	0
region_cfg_regwen_4_rd_A	376075937	1898	0	0
region_cfg_regwen_5_rd_A	376075937	1876	0	0
region_cfg_regwen_6_rd_A	376075937	1896	0	0
region_cfg_regwen_7_rd_A	376075937	1807	0	0
scratch_rd_A	376075937	2377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	4739	0	0
T66	31510	1	0	0
T67	70565	1	0	0
T212	5782	584	0	0
T213	3619	136	0	0
T214	4314	6	0	0
T222	3413	146	0	0
T230	2315	3	0	0
T231	5741	202	0	0
T232	4189	212	0	0
T234	4128	85	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2520	0	0
T235	10861	22	0	0
T244	10690	21	0	0
T245	5859	6	0	0
T261	103312	72	0	0
T277	146464	122	0	0
T278	5636	4	0	0
T279	9884	23	0	0
T280	10466	24	0	0
T281	11123	27	0	0
T282	10313	14	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2390	0	0
T235	10861	81	0	0
T244	10690	21	0	0
T245	5859	62	0	0
T261	103312	230	0	0
T277	146464	147	0	0
T278	5636	26	0	0
T279	9884	41	0	0
T280	10466	45	0	0
T281	11123	22	0	0
T282	10313	22	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3457	0	0
T235	10861	59	0	0
T244	10690	25	0	0
T245	5859	7	0	0
T261	103312	291	0	0
T277	146464	139	0	0
T278	5636	28	0	0
T279	9884	66	0	0
T280	10466	9	0	0
T281	11123	15	0	0
T282	10313	5	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2411	0	0
T235	10861	63	0	0
T244	10690	20	0	0
T245	5859	37	0	0
T261	103312	193	0	0
T277	146464	120	0	0
T278	5636	14	0	0
T279	9884	35	0	0
T280	10466	20	0	0
T281	11123	47	0	0
T283	3808	10	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2808	0	0
T235	10861	64	0	0
T244	10690	16	0	0
T245	5859	30	0	0
T261	103312	268	0	0
T277	146464	132	0	0
T278	5636	11	0	0
T279	9884	18	0	0
T280	10466	29	0	0
T281	11123	31	0	0
T282	10313	14	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3263	0	0
T235	10861	19	0	0
T244	10690	2	0	0
T245	5859	44	0	0
T261	103312	313	0	0
T262	80411	146	0	0
T277	146464	119	0	0
T278	5636	3	0	0
T279	9884	28	0	0
T282	10313	19	0	0
T283	3808	12	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3242	0	0
T235	10861	60	0	0
T244	10690	10	0	0
T245	5859	10	0	0
T261	103312	238	0	0
T277	146464	134	0	0
T278	5636	53	0	0
T279	9884	50	0	0
T280	10466	15	0	0
T281	11123	23	0	0
T282	10313	23	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2645	0	0
T235	10861	16	0	0
T244	10690	26	0	0
T245	5859	39	0	0
T261	103312	264	0	0
T277	146464	122	0	0
T278	5636	36	0	0
T279	9884	40	0	0
T280	10466	19	0	0
T281	11123	41	0	0
T282	10313	36	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2181	0	0
T235	10861	13	0	0
T244	10690	30	0	0
T245	5859	71	0	0
T261	103312	303	0	0
T277	146464	109	0	0
T278	5636	7	0	0
T279	9884	27	0	0
T280	10466	21	0	0
T281	11123	23	0	0
T282	10313	27	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2283	0	0
T235	10861	20	0	0
T244	10690	7	0	0
T245	5859	25	0	0
T261	103312	337	0	0
T277	146464	136	0	0
T278	5636	11	0	0
T279	9884	9	0	0
T280	10466	6	0	0
T281	11123	13	0	0
T282	10313	5	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2961	0	0
T235	10861	14	0	0
T244	10690	15	0	0
T245	5859	32	0	0
T261	103312	340	0	0
T277	146464	123	0	0
T278	5636	4	0	0
T279	9884	66	0	0
T280	10466	14	0	0
T281	11123	26	0	0
T282	10313	27	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1390	0	0
T235	10861	15	0	0
T244	10690	8	0	0
T245	5859	18	0	0
T261	103312	67	0	0
T262	80411	35	0	0
T277	146464	120	0	0
T278	5636	7	0	0
T279	9884	16	0	0
T281	11123	38	0	0
T282	10313	13	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2434	0	0
T235	10861	21	0	0
T244	10690	17	0	0
T245	5859	11	0	0
T261	103312	67	0	0
T277	146464	161	0	0
T278	5636	1	0	0
T279	9884	15	0	0
T280	10466	13	0	0
T281	11123	27	0	0
T282	10313	22	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1941	0	0
T235	10861	16	0	0
T244	10690	51	0	0
T245	5859	7	0	0
T261	103312	94	0	0
T277	146464	142	0	0
T278	5636	7	0	0
T279	9884	24	0	0
T280	10466	4	0	0
T281	11123	14	0	0
T282	10313	6	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2663	0	0
T235	10861	23	0	0
T244	10690	54	0	0
T245	5859	11	0	0
T261	103312	80	0	0
T277	146464	163	0	0
T278	5636	15	0	0
T279	9884	14	0	0
T280	10466	40	0	0
T281	11123	19	0	0
T282	10313	51	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2240	0	0
T235	10861	15	0	0
T244	10690	14	0	0
T245	5859	5	0	0
T261	103312	55	0	0
T277	146464	124	0	0
T278	5636	13	0	0
T279	9884	14	0	0
T280	10466	34	0	0
T281	11123	17	0	0
T282	10313	12	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2405	0	0
T235	10861	12	0	0
T244	10690	12	0	0
T245	5859	9	0	0
T261	103312	71	0	0
T262	80411	40	0	0
T277	146464	124	0	0
T278	5636	13	0	0
T279	9884	6	0	0
T280	10466	27	0	0
T282	10313	3	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2321	0	0
T235	10861	13	0	0
T244	10690	40	0	0
T245	5859	2	0	0
T261	103312	95	0	0
T277	146464	101	0	0
T278	5636	4	0	0
T279	9884	15	0	0
T280	10466	16	0	0
T281	11123	26	0	0
T282	10313	2	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1424	0	0
T235	10861	28	0	0
T244	10690	35	0	0
T245	5859	3	0	0
T261	103312	76	0	0
T277	146464	112	0	0
T278	5636	12	0	0
T279	9884	17	0	0
T280	10466	38	0	0
T281	11123	7	0	0
T282	10313	41	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2361	0	0
T235	10861	22	0	0
T244	10690	6	0	0
T245	5859	9	0	0
T261	103312	55	0	0
T277	146464	148	0	0
T278	5636	4	0	0
T279	9884	11	0	0
T280	10466	22	0	0
T281	11123	28	0	0
T282	10313	24	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2201	0	0
T235	10861	13	0	0
T244	10690	50	0	0
T245	5859	9	0	0
T261	103312	77	0	0
T277	146464	113	0	0
T278	5636	11	0	0
T279	9884	33	0	0
T280	10466	56	0	0
T281	11123	8	0	0
T282	10313	50	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2938	0	0
T235	10861	32	0	0
T244	10690	3	0	0
T245	5859	48	0	0
T261	103312	343	0	0
T277	146464	151	0	0
T278	5636	4	0	0
T279	9884	53	0	0
T280	10466	32	0	0
T281	11123	26	0	0
T282	10313	21	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1438	0	0
T235	10861	29	0	0
T244	10690	26	0	0
T245	5859	9	0	0
T261	103312	75	0	0
T262	80411	50	0	0
T277	146464	160	0	0
T278	5636	5	0	0
T279	9884	26	0	0
T280	10466	6	0	0
T282	10313	5	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3373	0	0
T235	10861	19	0	0
T244	10690	11	0	0
T245	5859	8	0	0
T261	103312	358	0	0
T277	146464	146	0	0
T278	5636	5	0	0
T279	9884	45	0	0
T280	10466	38	0	0
T281	11123	21	0	0
T282	10313	13	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3544	0	0
T235	10861	38	0	0
T244	10690	13	0	0
T245	5859	31	0	0
T261	103312	382	0	0
T277	146464	167	0	0
T278	5636	8	0	0
T279	9884	7	0	0
T280	10466	30	0	0
T281	11123	7	0	0
T282	10313	16	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1860	0	0
T235	10861	11	0	0
T244	10690	24	0	0
T245	5859	1	0	0
T261	103312	81	0	0
T277	146464	106	0	0
T278	5636	8	0	0
T279	9884	21	0	0
T280	10466	29	0	0
T281	11123	35	0	0
T282	10313	11	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1998	0	0
T235	10861	8	0	0
T244	10690	16	0	0
T245	5859	9	0	0
T261	103312	91	0	0
T277	146464	165	0	0
T278	5636	12	0	0
T279	9884	14	0	0
T280	10466	15	0	0
T281	11123	10	0	0
T282	10313	24	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3296	0	0
T235	10861	44	0	0
T244	10690	8	0	0
T245	5859	62	0	0
T261	103312	310	0	0
T277	146464	112	0	0
T278	5636	4	0	0
T279	9884	60	0	0
T280	10466	40	0	0
T281	11123	37	0	0
T282	10313	30	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3490	0	0
T235	10861	67	0	0
T244	10690	23	0	0
T245	5859	5	0	0
T261	103312	314	0	0
T277	146464	113	0	0
T278	5636	26	0	0
T279	9884	25	0	0
T280	10466	40	0	0
T281	11123	57	0	0
T282	10313	7	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2771	0	0
T235	10861	32	0	0
T244	10690	47	0	0
T245	5859	56	0	0
T261	103312	255	0	0
T277	146464	135	0	0
T278	5636	13	0	0
T279	9884	45	0	0
T280	10466	38	0	0
T281	11123	30	0	0
T282	10313	24	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2717	0	0
T235	10861	13	0	0
T244	10690	21	0	0
T245	5859	8	0	0
T261	103312	300	0	0
T277	146464	126	0	0
T278	5636	36	0	0
T279	9884	16	0	0
T280	10466	19	0	0
T281	11123	15	0	0
T282	10313	6	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3195	0	0
T235	10861	13	0	0
T244	10690	30	0	0
T245	5859	22	0	0
T261	103312	289	0	0
T277	146464	163	0	0
T278	5636	40	0	0
T279	9884	53	0	0
T280	10466	52	0	0
T281	11123	51	0	0
T282	10313	32	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2820	0	0
T235	10861	63	0	0
T244	10690	48	0	0
T245	5859	15	0	0
T261	103312	352	0	0
T262	80411	138	0	0
T277	146464	122	0	0
T278	5636	50	0	0
T279	9884	67	0	0
T280	10466	6	0	0
T281	11123	3	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3161	0	0
T235	10861	13	0	0
T244	10690	50	0	0
T245	5859	16	0	0
T261	103312	167	0	0
T277	146464	129	0	0
T278	5636	34	0	0
T279	9884	84	0	0
T280	10466	1	0	0
T281	11123	19	0	0
T282	10313	57	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3471	0	0
T235	10861	27	0	0
T244	10690	53	0	0
T245	5859	38	0	0
T261	103312	290	0	0
T277	146464	121	0	0
T278	5636	1	0	0
T279	9884	49	0	0
T280	10466	9	0	0
T281	11123	31	0	0
T282	10313	8	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3539	0	0
T235	10861	37	0	0
T244	10690	23	0	0
T245	5859	42	0	0
T261	103312	267	0	0
T277	146464	132	0	0
T278	5636	11	0	0
T279	9884	43	0	0
T280	10466	10	0	0
T281	11123	12	0	0
T282	10313	28	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3104	0	0
T235	10861	40	0	0
T245	5859	40	0	0
T261	103312	325	0	0
T262	80411	252	0	0
T277	146464	126	0	0
T279	9884	48	0	0
T280	10466	30	0	0
T281	11123	30	0	0
T282	10313	6	0	0
T284	11169	24	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1334	0	0
T235	10861	15	0	0
T244	10690	27	0	0
T245	5859	16	0	0
T261	103312	69	0	0
T277	146464	113	0	0
T278	5636	6	0	0
T279	9884	19	0	0
T280	10466	9	0	0
T281	11123	2	0	0
T282	10313	24	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1823	0	0
T235	10861	15	0	0
T244	10690	25	0	0
T245	5859	10	0	0
T261	103312	68	0	0
T277	146464	123	0	0
T278	5636	12	0	0
T279	9884	19	0	0
T280	10466	19	0	0
T281	11123	49	0	0
T282	10313	12	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2104	0	0
T235	10861	11	0	0
T244	10690	38	0	0
T245	5859	5	0	0
T261	103312	76	0	0
T277	146464	167	0	0
T278	5636	11	0	0
T279	9884	11	0	0
T280	10466	51	0	0
T281	11123	63	0	0
T282	10313	22	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2398	0	0
T235	10861	17	0	0
T244	10690	20	0	0
T245	5859	2	0	0
T261	103312	91	0	0
T277	146464	176	0	0
T278	5636	10	0	0
T279	9884	11	0	0
T280	10466	18	0	0
T281	11123	21	0	0
T282	10313	16	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1967	0	0
T235	10861	5	0	0
T244	10690	42	0	0
T245	5859	9	0	0
T261	103312	98	0	0
T277	146464	117	0	0
T278	5636	10	0	0
T279	9884	11	0	0
T280	10466	7	0	0
T281	11123	62	0	0
T282	10313	23	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2371	0	0
T235	10861	28	0	0
T244	10690	20	0	0
T245	5859	11	0	0
T261	103312	90	0	0
T277	146464	141	0	0
T278	5636	9	0	0
T279	9884	12	0	0
T280	10466	23	0	0
T281	11123	4	0	0
T282	10313	13	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1924	0	0
T235	10861	21	0	0
T244	10690	12	0	0
T245	5859	13	0	0
T261	103312	81	0	0
T277	146464	148	0	0
T278	5636	9	0	0
T279	9884	20	0	0
T280	10466	5	0	0
T281	11123	22	0	0
T282	10313	33	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2379	0	0
T235	10861	14	0	0
T244	10690	6	0	0
T245	5859	13	0	0
T261	103312	71	0	0
T277	146464	152	0	0
T278	5636	8	0	0
T279	9884	21	0	0
T280	10466	7	0	0
T281	11123	11	0	0
T282	10313	30	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1406	0	0
T235	10861	23	0	0
T244	10690	50	0	0
T245	5859	5	0	0
T261	103312	70	0	0
T277	146464	162	0	0
T278	5636	12	0	0
T279	9884	13	0	0
T280	10466	23	0	0
T281	11123	33	0	0
T282	10313	27	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1801	0	0
T235	10861	5	0	0
T244	10690	46	0	0
T245	5859	17	0	0
T261	103312	73	0	0
T277	146464	117	0	0
T278	5636	3	0	0
T279	9884	10	0	0
T280	10466	18	0	0
T281	11123	7	0	0
T282	10313	22	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3165	0	0
T235	10861	78	0	0
T244	10690	16	0	0
T245	5859	9	0	0
T261	103312	299	0	0
T277	146464	112	0	0
T278	5636	31	0	0
T279	9884	11	0	0
T280	10466	32	0	0
T281	11123	14	0	0
T282	10313	54	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2509	0	0
T235	10861	19	0	0
T244	10690	13	0	0
T245	5859	4	0	0
T261	103312	87	0	0
T277	146464	142	0	0
T278	5636	10	0	0
T279	9884	17	0	0
T280	10466	19	0	0
T281	11123	9	0	0
T282	10313	31	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3657	0	0
T235	10861	19	0	0
T244	10690	39	0	0
T245	5859	58	0	0
T261	103312	354	0	0
T277	146464	180	0	0
T278	5636	8	0	0
T279	9884	70	0	0
T280	10466	70	0	0
T281	11123	25	0	0
T282	10313	9	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3330	0	0
T235	10861	77	0	0
T244	10690	35	0	0
T245	5859	31	0	0
T261	103312	321	0	0
T277	146464	122	0	0
T278	5636	11	0	0
T279	9884	11	0	0
T280	10466	45	0	0
T281	11123	37	0	0
T282	10313	50	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1993	0	0
T235	10861	12	0	0
T244	10690	32	0	0
T245	5859	7	0	0
T261	103312	69	0	0
T262	80411	36	0	0
T277	146464	131	0	0
T278	5636	10	0	0
T279	9884	14	0	0
T280	10466	3	0	0
T281	11123	41	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2495	0	0
T235	10861	18	0	0
T244	10690	40	0	0
T245	5859	6	0	0
T261	103312	71	0	0
T262	80411	35	0	0
T277	146464	99	0	0
T278	5636	5	0	0
T279	9884	15	0	0
T280	10466	10	0	0
T281	11123	32	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2497	0	0
T235	10861	7	0	0
T244	10690	34	0	0
T245	5859	11	0	0
T261	103312	75	0	0
T277	146464	153	0	0
T278	5636	2	0	0
T279	9884	16	0	0
T280	10466	37	0	0
T281	11123	37	0	0
T282	10313	23	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2195	0	0
T235	10861	34	0	0
T244	10690	5	0	0
T245	5859	2	0	0
T261	103312	227	0	0
T277	146464	114	0	0
T278	5636	1	0	0
T279	9884	39	0	0
T280	10466	21	0	0
T281	11123	14	0	0
T282	10313	6	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2459	0	0
T235	10861	9	0	0
T244	10690	3	0	0
T245	5859	6	0	0
T261	103312	73	0	0
T277	146464	186	0	0
T278	5636	9	0	0
T279	9884	7	0	0
T280	10466	28	0	0
T281	11123	21	0	0
T282	10313	26	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2713	0	0
T235	10861	9	0	0
T244	10690	24	0	0
T245	5859	7	0	0
T261	103312	147	0	0
T277	146464	107	0	0
T278	5636	17	0	0
T279	9884	30	0	0
T280	10466	12	0	0
T281	11123	17	0	0
T282	10313	44	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1521	0	0
T235	10861	27	0	0
T244	10690	26	0	0
T245	5859	13	0	0
T261	103312	70	0	0
T277	146464	137	0	0
T278	5636	15	0	0
T279	9884	15	0	0
T280	10466	15	0	0
T281	11123	18	0	0
T282	10313	44	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2667	0	0
T235	10861	25	0	0
T244	10690	42	0	0
T245	5859	20	0	0
T261	103312	148	0	0
T277	146464	123	0	0
T278	5636	18	0	0
T279	9884	22	0	0
T280	10466	34	0	0
T281	11123	12	0	0
T282	10313	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2651	0	0
T235	10861	32	0	0
T245	5859	22	0	0
T261	103312	211	0	0
T277	146464	171	0	0
T278	5636	17	0	0
T279	9884	38	0	0
T280	10466	36	0	0
T281	11123	51	0	0
T282	10313	26	0	0
T283	3808	14	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1937	0	0
T235	10861	16	0	0
T244	10690	4	0	0
T245	5859	14	0	0
T261	103312	86	0	0
T277	146464	146	0	0
T278	5636	9	0	0
T279	9884	8	0	0
T280	10466	27	0	0
T281	11123	14	0	0
T282	10313	29	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2595	0	0
T235	10861	12	0	0
T244	10690	8	0	0
T245	5859	23	0	0
T261	103312	98	0	0
T277	146464	119	0	0
T278	5636	4	0	0
T279	9884	27	0	0
T281	11123	22	0	0
T282	10313	14	0	0
T283	3808	1	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2120	0	0
T235	10861	19	0	0
T244	10690	30	0	0
T245	5859	14	0	0
T261	103312	131	0	0
T277	146464	140	0	0
T278	5636	12	0	0
T279	9884	17	0	0
T280	10466	14	0	0
T281	11123	12	0	0
T282	10313	32	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2617	0	0
T235	10861	20	0	0
T244	10690	5	0	0
T245	5859	10	0	0
T261	103312	121	0	0
T277	146464	89	0	0
T278	5636	3	0	0
T279	9884	34	0	0
T280	10466	2	0	0
T281	11123	24	0	0
T282	10313	25	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2546	0	0
T235	10861	15	0	0
T244	10690	3	0	0
T245	5859	16	0	0
T261	103312	102	0	0
T277	146464	148	0	0
T278	5636	11	0	0
T279	9884	25	0	0
T280	10466	26	0	0
T281	11123	9	0	0
T282	10313	4	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2324	0	0
T235	10861	21	0	0
T244	10690	31	0	0
T245	5859	11	0	0
T261	103312	98	0	0
T277	146464	154	0	0
T278	5636	15	0	0
T279	9884	21	0	0
T280	10466	36	0	0
T281	11123	28	0	0
T282	10313	36	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2455	0	0
T235	10861	18	0	0
T245	5859	14	0	0
T261	103312	88	0	0
T277	146464	168	0	0
T278	5636	7	0	0
T279	9884	22	0	0
T280	10466	27	0	0
T281	11123	8	0	0
T282	10313	17	0	0
T283	3808	8	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2037	0	0
T235	10861	22	0	0
T244	10690	45	0	0
T245	5859	19	0	0
T261	103312	105	0	0
T277	146464	122	0	0
T278	5636	8	0	0
T279	9884	9	0	0
T280	10466	35	0	0
T281	11123	14	0	0
T282	10313	10	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3376	0	0
T235	10861	40	0	0
T244	10690	24	0	0
T245	5859	2	0	0
T261	103312	251	0	0
T277	146464	146	0	0
T278	5636	32	0	0
T279	9884	56	0	0
T280	10466	45	0	0
T281	11123	51	0	0
T282	10313	12	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3463	0	0
T235	10861	51	0	0
T244	10690	27	0	0
T245	5859	37	0	0
T261	103312	313	0	0
T277	146464	188	0	0
T278	5636	34	0	0
T279	9884	51	0	0
T280	10466	29	0	0
T281	11123	4	0	0
T282	10313	24	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3516	0	0
T235	10861	28	0	0
T244	10690	43	0	0
T245	5859	11	0	0
T261	103312	397	0	0
T277	146464	130	0	0
T278	5636	7	0	0
T279	9884	41	0	0
T280	10466	29	0	0
T281	11123	26	0	0
T282	10313	4	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2753	0	0
T235	10861	51	0	0
T244	10690	31	0	0
T245	5859	40	0	0
T261	103312	330	0	0
T277	146464	108	0	0
T278	5636	41	0	0
T279	9884	33	0	0
T280	10466	29	0	0
T281	11123	2	0	0
T282	10313	22	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2515	0	0
T235	10861	79	0	0
T244	10690	29	0	0
T245	5859	7	0	0
T261	103312	431	0	0
T277	146464	144	0	0
T278	5636	4	0	0
T279	9884	17	0	0
T280	10466	43	0	0
T281	11123	15	0	0
T282	10313	8	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3381	0	0
T235	10861	44	0	0
T244	10690	24	0	0
T245	5859	10	0	0
T261	103312	361	0	0
T277	146464	98	0	0
T278	5636	13	0	0
T279	9884	42	0	0
T280	10466	16	0	0
T281	11123	10	0	0
T282	10313	2	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	3280	0	0
T235	10861	74	0	0
T244	10690	18	0	0
T245	5859	1	0	0
T261	103312	255	0	0
T277	146464	161	0	0
T278	5636	7	0	0
T279	9884	52	0	0
T280	10466	42	0	0
T281	11123	33	0	0
T282	10313	18	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2814	0	0
T235	10861	52	0	0
T244	10690	35	0	0
T245	5859	33	0	0
T261	103312	295	0	0
T262	80411	156	0	0
T277	146464	124	0	0
T278	5636	40	0	0
T279	9884	14	0	0
T280	10466	13	0	0
T284	11169	41	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1171	0	0
T235	10861	5	0	0
T244	10690	14	0	0
T278	5636	4	0	0
T279	9884	10	0	0
T280	10466	11	0	0
T281	11123	1	0	0
T282	10313	18	0	0
T284	11169	20	0	0
T285	12017	26	0	0
T286	10432	8	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2438	0	0
T235	10861	19	0	0
T244	10690	42	0	0
T245	5859	6	0	0
T261	103312	61	0	0
T277	146464	99	0	0
T278	5636	9	0	0
T279	9884	13	0	0
T280	10466	37	0	0
T281	11123	10	0	0
T282	10313	13	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2409	0	0
T235	10861	9	0	0
T244	10690	47	0	0
T245	5859	10	0	0
T261	103312	92	0	0
T277	146464	145	0	0
T278	5636	8	0	0
T279	9884	15	0	0
T280	10466	13	0	0
T281	11123	12	0	0
T282	10313	26	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2438	0	0
T235	10861	10	0	0
T244	10690	36	0	0
T245	5859	9	0	0
T261	103312	91	0	0
T277	146464	181	0	0
T278	5636	3	0	0
T279	9884	25	0	0
T280	10466	24	0	0
T281	11123	13	0	0
T282	10313	19	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1937	0	0
T235	10861	17	0	0
T244	10690	16	0	0
T245	5859	9	0	0
T261	103312	61	0	0
T277	146464	120	0	0
T278	5636	5	0	0
T279	9884	19	0	0
T280	10466	11	0	0
T281	11123	6	0	0
T282	10313	17	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1898	0	0
T235	10861	14	0	0
T244	10690	45	0	0
T245	5859	13	0	0
T261	103312	83	0	0
T277	146464	132	0	0
T278	5636	8	0	0
T279	9884	24	0	0
T281	11123	11	0	0
T282	10313	12	0	0
T283	3808	2	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1876	0	0
T235	10861	11	0	0
T244	10690	3	0	0
T245	5859	1	0	0
T261	103312	69	0	0
T277	146464	154	0	0
T278	5636	7	0	0
T279	9884	14	0	0
T280	10466	32	0	0
T281	11123	16	0	0
T282	10313	6	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1896	0	0
T235	10861	7	0	0
T244	10690	2	0	0
T245	5859	8	0	0
T261	103312	92	0	0
T262	80411	56	0	0
T277	146464	126	0	0
T278	5636	11	0	0
T279	9884	17	0	0
T280	10466	39	0	0
T282	10313	31	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	1807	0	0
T235	10861	17	0	0
T244	10690	24	0	0
T245	5859	4	0	0
T261	103312	94	0	0
T277	146464	157	0	0
T278	5636	7	0	0
T279	9884	22	0	0
T280	10466	8	0	0
T281	11123	16	0	0
T282	10313	17	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376075937	2377	0	0
T235	10861	20	0	0
T244	10690	9	0	0
T245	5859	7	0	0
T261	103312	82	0	0
T277	146464	137	0	0
T278	5636	5	0	0
T279	9884	18	0	0
T280	10466	42	0	0
T281	11123	22	0	0
T282	10313	9	0	0