Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23632212	1		T1	4820		T2	9318		T3	943
full_word	7866794	1		T1	3565		T2	9500		T3	45

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31498706	1		T1	8385		T2	18818		T3	988
auto[TlIntgErrCmd]	116	1		T63	3		T196	9		T197	3
auto[TlIntgErrData]	95	1		T63	5		T196	7		T197	5
auto[TlIntgErrBoth]	89	1		T63	2		T196	4		T197	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26976336	1		T1	5748		T2	11022		T3	941
auto[1]	4522670	1		T1	2637		T2	7796		T3	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22906663	1		T1	4482		T2	8381		T3	940
auto[TlIntgErrNone]	partial	auto[1]	725269	1		T1	338		T2	937		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	4069537	1		T1	1266		T2	2641		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3797237	1		T1	2299		T2	6859		T3	44
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T63	2		T196	5		T197	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T63	1		T196	3		T291	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T345	3		T349	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T196	1		T344	1		T343	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T63	1		T196	6		T197	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T63	3		T196	1		T197	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T63	1		T347	1		T343	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T294	1		T350	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T63	1		T196	2		T197	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T63	1		T196	2		T197	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T347	1		T351	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T342	1		T346	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21273	1		T194	791		T195	680		T63	10
full_word	4107805	1		T3	16524		T5	16037		T18	140

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4128797	1		T3	16524		T5	16037		T18	140
auto[TlIntgErrCmd]	86	1		T63	3		T196	5		T197	2
auto[TlIntgErrData]	95	1		T63	4		T196	5		T197	5
auto[TlIntgErrBoth]	100	1		T63	3		T196	8		T197	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4102310	1		T3	16524		T5	16037		T18	140
auto[1]	26768	1		T194	961		T195	775		T63	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1197	1		T194	50		T224	120		T240	6
auto[TlIntgErrNone]	partial	auto[1]	19815	1		T194	741		T195	680		T224	1077
auto[TlIntgErrNone]	full_word	auto[0]	4100993	1		T3	16524		T5	16037		T18	140
auto[TlIntgErrNone]	full_word	auto[1]	6792	1		T194	220		T195	95		T224	598
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T63	1		T196	1		T291	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T63	2		T196	1		T197	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T196	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T196	2		T295	1		T344	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T63	3		T196	1		T197	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T63	1		T196	4		T197	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T291	1		T295	1		T348	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T344	1		T342	1		T346	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T63	2		T196	3		T291	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T63	1		T196	3		T197	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T196	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T196	1		T294	1		T344	1