Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 0 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T2,T3
11CoveredT3,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 1528887124 1525715600 0 0
CheckNGreaterZero_A 4124 4124 0 0
GntImpliesReady_A 1528887124 398434941 0 0
GntImpliesValid_A 1528887124 398434941 0 0
GrantKnown_A 1528887124 1525715600 0 0
IdxKnown_A 1528887124 1525715600 0 0
IndexIsCorrect_A 1528887124 398434941 0 0
NoReadyValidNoGrant_A 1528887124 176647942 0 0
Priority_A 1528887124 423188817 0 0
ReadyAndValidImplyGrant_A 1528887124 398434941 0 0
ReqAndReadyImplyGrant_A 1528887124 398434941 0 0
ReqImpliesValid_A 1528887124 423188817 0 0
ValidKnown_A 1528887124 1525715600 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 1525715600 0 0
T1 380980 366444 0 0
T2 836388 836120 0 0
T3 2260444 2259844 0 0
T4 839472 839252 0 0
T5 271172 270632 0 0
T6 21296 20976 0 0
T10 15264 12724 0 0
T17 304788 304404 0 0
T18 98072 92780 0 0
T19 839600 839328 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4124 4124 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T10 4 4 0 0
T17 4 4 0 0
T18 4 4 0 0
T19 4 4 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 398434941 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 33130 0 0
T4 839472 90314 0 0
T5 271172 44640 0 0
T6 21296 5854 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 31940 0 0
T35 186994 59420 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 398434941 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 33130 0 0
T4 839472 90314 0 0
T5 271172 44640 0 0
T6 21296 5854 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 31940 0 0
T35 186994 59420 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 1525715600 0 0
T1 380980 366444 0 0
T2 836388 836120 0 0
T3 2260444 2259844 0 0
T4 839472 839252 0 0
T5 271172 270632 0 0
T6 21296 20976 0 0
T10 15264 12724 0 0
T17 304788 304404 0 0
T18 98072 92780 0 0
T19 839600 839328 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 1525715600 0 0
T1 380980 366444 0 0
T2 836388 836120 0 0
T3 2260444 2259844 0 0
T4 839472 839252 0 0
T5 271172 270632 0 0
T6 21296 20976 0 0
T10 15264 12724 0 0
T17 304788 304404 0 0
T18 98072 92780 0 0
T19 839600 839328 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 398434941 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 33130 0 0
T4 839472 90314 0 0
T5 271172 44640 0 0
T6 21296 5854 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 31940 0 0
T35 186994 59420 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 176647942 0 0
T1 190490 16968 0 0
T2 836388 7448 0 0
T3 2260444 1231986 0 0
T4 839472 7516 0 0
T5 271172 129412 0 0
T6 21296 720 0 0
T10 15264 1536 0 0
T17 304788 1534 0 0
T18 98072 5212 0 0
T19 839600 7636 0 0
T20 0 1011724 0 0
T35 186994 506 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 423188817 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 477378 0 0
T4 839472 90314 0 0
T5 271172 47996 0 0
T6 21296 5870 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 308606 0 0
T35 186994 59420 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 398434941 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 33130 0 0
T4 839472 90314 0 0
T5 271172 44640 0 0
T6 21296 5854 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 31940 0 0
T35 186994 59420 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 398434941 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 33130 0 0
T4 839472 90314 0 0
T5 271172 44640 0 0
T6 21296 5854 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 31940 0 0
T35 186994 59420 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 423188817 0 0
T1 190490 60516 0 0
T2 836388 89570 0 0
T3 2260444 477378 0 0
T4 839472 90314 0 0
T5 271172 47996 0 0
T6 21296 5870 0 0
T10 15264 390 0 0
T17 304788 145994 0 0
T18 98072 1872 0 0
T19 839600 90050 0 0
T20 0 308606 0 0
T35 186994 59420 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528887124 1525715600 0 0
T1 380980 366444 0 0
T2 836388 836120 0 0
T3 2260444 2259844 0 0
T4 839472 839252 0 0
T5 271172 270632 0 0
T6 21296 20976 0 0
T10 15264 12724 0 0
T17 304788 304404 0 0
T18 98072 92780 0 0
T19 839600 839328 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 0 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T2,T3
11CoveredT3,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 382221781 381428900 0 0
CheckNGreaterZero_A 1031 1031 0 0
GntImpliesReady_A 382221781 104914695 0 0
GntImpliesValid_A 382221781 104914695 0 0
GrantKnown_A 382221781 381428900 0 0
IdxKnown_A 382221781 381428900 0 0
IndexIsCorrect_A 382221781 104914695 0 0
NoReadyValidNoGrant_A 382221781 45909542 0 0
Priority_A 382221781 111149873 0 0
ReadyAndValidImplyGrant_A 382221781 104914695 0 0
ReqAndReadyImplyGrant_A 382221781 104914695 0 0
ReqImpliesValid_A 382221781 111149873 0 0
ValidKnown_A 382221781 381428900 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914695 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914695 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914695 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 45909542 0 0
T1 95245 8484 0 0
T2 209097 1924 0 0
T3 565111 311178 0 0
T4 209868 1772 0 0
T5 67793 40167 0 0
T6 5324 249 0 0
T10 3816 768 0 0
T17 76197 359 0 0
T18 24518 2583 0 0
T19 209900 2138 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 111149873 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 131213 0 0
T4 209868 20909 0 0
T5 67793 14859 0 0
T6 5324 1545 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914695 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914695 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 111149873 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 131213 0 0
T4 209868 20909 0 0
T5 67793 14859 0 0
T6 5324 1545 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 0 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T18
1CoveredT1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T2,T3
11CoveredT3,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T18


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 382221781 381428900 0 0
CheckNGreaterZero_A 1031 1031 0 0
GntImpliesReady_A 382221781 104914620 0 0
GntImpliesValid_A 382221781 104914620 0 0
GrantKnown_A 382221781 381428900 0 0
IdxKnown_A 382221781 381428900 0 0
IndexIsCorrect_A 382221781 104914620 0 0
NoReadyValidNoGrant_A 382221781 45909542 0 0
Priority_A 382221781 111149798 0 0
ReadyAndValidImplyGrant_A 382221781 104914620 0 0
ReqAndReadyImplyGrant_A 382221781 104914620 0 0
ReqImpliesValid_A 382221781 111149798 0 0
ValidKnown_A 382221781 381428900 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914620 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914620 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914620 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 45909542 0 0
T1 95245 8484 0 0
T2 209097 1924 0 0
T3 565111 311178 0 0
T4 209868 1772 0 0
T5 67793 40167 0 0
T6 5324 249 0 0
T10 3816 768 0 0
T17 76197 359 0 0
T18 24518 2583 0 0
T19 209900 2138 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 111149798 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 131213 0 0
T4 209868 20909 0 0
T5 67793 14859 0 0
T6 5324 1545 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914620 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 104914620 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 8576 0 0
T4 209868 20909 0 0
T5 67793 14355 0 0
T6 5324 1540 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 111149798 0 0
T1 95245 30258 0 0
T2 209097 22270 0 0
T3 565111 131213 0 0
T4 209868 20909 0 0
T5 67793 14859 0 0
T6 5324 1545 0 0
T10 3816 195 0 0
T17 76197 68449 0 0
T18 24518 820 0 0
T19 209900 24726 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 0 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T17,T4
10CoveredT3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT2,T17,T4
11CoveredT3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT2,T17,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT2,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 382221781 381428900 0 0
CheckNGreaterZero_A 1031 1031 0 0
GntImpliesReady_A 382221781 94302813 0 0
GntImpliesValid_A 382221781 94302813 0 0
GrantKnown_A 382221781 381428900 0 0
IdxKnown_A 382221781 381428900 0 0
IndexIsCorrect_A 382221781 94302813 0 0
NoReadyValidNoGrant_A 382221781 42414429 0 0
Priority_A 382221781 100444573 0 0
ReadyAndValidImplyGrant_A 382221781 94302813 0 0
ReqAndReadyImplyGrant_A 382221781 94302813 0 0
ReqImpliesValid_A 382221781 100444573 0 0
ValidKnown_A 382221781 381428900 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 42414429 0 0
T2 209097 1800 0 0
T3 565111 304815 0 0
T4 209868 1986 0 0
T5 67793 24539 0 0
T6 5324 111 0 0
T10 3816 0 0 0
T17 76197 408 0 0
T18 24518 23 0 0
T19 209900 1680 0 0
T20 0 505862 0 0
T35 93497 253 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 100444573 0 0
T2 209097 22515 0 0
T3 565111 107476 0 0
T4 209868 24248 0 0
T5 67793 9139 0 0
T6 5324 1390 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 154303 0 0
T35 93497 29710 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 100444573 0 0
T2 209097 22515 0 0
T3 565111 107476 0 0
T4 209868 24248 0 0
T5 67793 9139 0 0
T6 5324 1390 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 154303 0 0
T35 93497 29710 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 0 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T17,T4
10CoveredT3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT2,T17,T4
11CoveredT3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT2,T17,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT2,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 382221781 381428900 0 0
CheckNGreaterZero_A 1031 1031 0 0
GntImpliesReady_A 382221781 94302813 0 0
GntImpliesValid_A 382221781 94302813 0 0
GrantKnown_A 382221781 381428900 0 0
IdxKnown_A 382221781 381428900 0 0
IndexIsCorrect_A 382221781 94302813 0 0
NoReadyValidNoGrant_A 382221781 42414429 0 0
Priority_A 382221781 100444573 0 0
ReadyAndValidImplyGrant_A 382221781 94302813 0 0
ReqAndReadyImplyGrant_A 382221781 94302813 0 0
ReqImpliesValid_A 382221781 100444573 0 0
ValidKnown_A 382221781 381428900 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 42414429 0 0
T2 209097 1800 0 0
T3 565111 304815 0 0
T4 209868 1986 0 0
T5 67793 24539 0 0
T6 5324 111 0 0
T10 3816 0 0 0
T17 76197 408 0 0
T18 24518 23 0 0
T19 209900 1680 0 0
T20 0 505862 0 0
T35 93497 253 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 100444573 0 0
T2 209097 22515 0 0
T3 565111 107476 0 0
T4 209868 24248 0 0
T5 67793 9139 0 0
T6 5324 1390 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 154303 0 0
T35 93497 29710 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 94302813 0 0
T2 209097 22515 0 0
T3 565111 7989 0 0
T4 209868 24248 0 0
T5 67793 7965 0 0
T6 5324 1387 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 15970 0 0
T35 93497 29710 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 100444573 0 0
T2 209097 22515 0 0
T3 565111 107476 0 0
T4 209868 24248 0 0
T5 67793 9139 0 0
T6 5324 1390 0 0
T10 3816 0 0 0
T17 76197 4548 0 0
T18 24518 116 0 0
T19 209900 20299 0 0
T20 0 154303 0 0
T35 93497 29710 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 382221781 381428900 0 0
T1 95245 91611 0 0
T2 209097 209030 0 0
T3 565111 564961 0 0
T4 209868 209813 0 0
T5 67793 67658 0 0
T6 5324 5244 0 0
T10 3816 3181 0 0
T17 76197 76101 0 0
T18 24518 23195 0 0
T19 209900 209832 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%