Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20395	1		T65	9		T67	8		T187	750
full_word	4040777	1		T1	26974		T2	16857		T17	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4060913	1		T1	26974		T2	16857		T17	6
auto[TlIntgErrCmd]	94	1		T65	3		T67	5		T236	4
auto[TlIntgErrData]	88	1		T65	4		T67	4		T236	4
auto[TlIntgErrBoth]	77	1		T65	3		T67	1		T236	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4035363	1		T1	26974		T2	16857		T17	6
auto[1]	25809	1		T65	8		T67	10		T187	884

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1351	1		T187	62		T221	56		T237	21
auto[TlIntgErrNone]	partial	auto[1]	18811	1		T187	688		T221	1178		T186	31
auto[TlIntgErrNone]	full_word	auto[0]	4033907	1		T1	26974		T2	16857		T17	6
auto[TlIntgErrNone]	full_word	auto[1]	6844	1		T187	196		T221	427		T186	5
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T236	1		T240	3		T254	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T65	2		T67	3		T236	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T65	1		T236	1		T254	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T67	2		T240	2		T302	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T65	1		T236	2		T254	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T65	3		T67	4		T236	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T358	1		T359	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T236	1		T254	1		T271	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T236	1		T240	3		T254	2
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T65	3		T67	1		T236	1
auto[TlIntgErrBoth]	full_word	auto[0]	8	1		T271	1		T357	1		T360	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27397903	1		T1	150287		T2	11249		T3	8141
full_word	7776198	1		T1	32908		T2	8351		T3	13233

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35173831	1		T1	183195		T2	19600		T3	21374
auto[TlIntgErrCmd]	94	1		T65	3		T67	3		T236	3
auto[TlIntgErrData]	93	1		T65	4		T67	2		T236	2
auto[TlIntgErrBoth]	83	1		T65	3		T67	5		T236	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30593081	1		T1	164519		T2	16521		T3	15227
auto[1]	4581020	1		T1	18676		T2	3079		T3	6147

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26686568	1		T1	147312		T2	10429		T3	7895
auto[TlIntgErrNone]	partial	auto[1]	711091	1		T1	2975		T2	820		T3	246
auto[TlIntgErrNone]	full_word	auto[0]	3906398	1		T1	17207		T2	6092		T3	7332
auto[TlIntgErrNone]	full_word	auto[1]	3869774	1		T1	15701		T2	2259		T3	5901
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T67	1		T236	1		T240	5
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T65	2		T67	2		T236	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T356	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T65	1		T240	2		T247	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T65	2		T67	1		T236	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T65	2		T67	1		T240	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T247	1		T361	1		T302	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T240	1		T247	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T65	1		T67	1		T240	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T65	2		T67	4		T236	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T271	1		T355	1		T255	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T236	1		T256	1		T356	1