Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1495699752	1492147872	0	0
CheckNGreaterZero_A	4112	4112	0	0
GntImpliesReady_A	1495699752	408420115	0	0
GntImpliesValid_A	1495699752	408420115	0	0
GrantKnown_A	1495699752	1492147872	0	0
IdxKnown_A	1495699752	1492147872	0	0
IndexIsCorrect_A	1495699752	408420115	0	0
NoReadyValidNoGrant_A	1495699752	175647207	0	0
Priority_A	1495699752	431947422	0	0
ReadyAndValidImplyGrant_A	1495699752	408420115	0	0
ReqAndReadyImplyGrant_A	1495699752	408420115	0	0
ReqImpliesValid_A	1495699752	431947422	0	0
ValidKnown_A	1495699752	1492147872	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	1492147872	0	0
T1	1494728	1494344	0	0
T2	199448	199148	0	0
T3	178244	177968	0	0
T4	95352	91000	0	0
T11	1705188	1705124	0	0
T12	15980	13016	0	0
T17	7864	7164	0	0
T18	5644	4836	0	0
T19	341540	320856	0	0
T20	6040	5288	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4112	4112	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	408420115	0	0
T1	1494728	459910	0	0
T2	199448	43574	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	408420115	0	0
T1	1494728	459910	0	0
T2	199448	43574	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	1492147872	0	0
T1	1494728	1494344	0	0
T2	199448	199148	0	0
T3	178244	177968	0	0
T4	95352	91000	0	0
T11	1705188	1705124	0	0
T12	15980	13016	0	0
T17	7864	7164	0	0
T18	5644	4836	0	0
T19	341540	320856	0	0
T20	6040	5288	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	1492147872	0	0
T1	1494728	1494344	0	0
T2	199448	199148	0	0
T3	178244	177968	0	0
T4	95352	91000	0	0
T11	1705188	1705124	0	0
T12	15980	13016	0	0
T17	7864	7164	0	0
T18	5644	4836	0	0
T19	341540	320856	0	0
T20	6040	5288	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	408420115	0	0
T1	1494728	459910	0	0
T2	199448	43574	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	175647207	0	0
T1	1494728	314412	0	0
T2	199448	70450	0	0
T3	178244	5248	0	0
T4	95352	4014	0	0
T5	0	3612	0	0
T7	0	576464	0	0
T11	1705188	2109968	0	0
T12	15980	1408	0	0
T15	0	1048576	0	0
T17	7864	846	0	0
T18	5644	528	0	0
T19	341540	25432	0	0
T20	6040	862	0	0
T58	0	1580	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	431947422	0	0
T1	1494728	512120	0	0
T2	199448	53756	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	408420115	0	0
T1	1494728	459910	0	0
T2	199448	43574	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	408420115	0	0
T1	1494728	459910	0	0
T2	199448	43574	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	431947422	0	0
T1	1494728	512120	0	0
T2	199448	53756	0	0
T3	178244	2632	0	0
T4	95352	5628	0	0
T5	0	61416	0	0
T6	0	28654	0	0
T11	1705188	514658	0	0
T12	15980	364	0	0
T15	0	255794	0	0
T17	7864	846	0	0
T18	5644	132	0	0
T19	341540	105200	0	0
T20	6040	394	0	0
T58	0	159390	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495699752	1492147872	0	0
T1	1494728	1494344	0	0
T2	199448	199148	0	0
T3	178244	177968	0	0
T4	95352	91000	0	0
T11	1705188	1705124	0	0
T12	15980	13016	0	0
T17	7864	7164	0	0
T18	5644	4836	0	0
T19	341540	320856	0	0
T20	6040	5288	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373924938	373036968	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	373924938	105067020	0	0
GntImpliesValid_A	373924938	105067020	0	0
GrantKnown_A	373924938	373036968	0	0
IdxKnown_A	373924938	373036968	0	0
IndexIsCorrect_A	373924938	105067020	0	0
NoReadyValidNoGrant_A	373924938	45026190	0	0
Priority_A	373924938	110891927	0	0
ReadyAndValidImplyGrant_A	373924938	105067020	0	0
ReqAndReadyImplyGrant_A	373924938	105067020	0	0
ReqImpliesValid_A	373924938	110891927	0	0
ValidKnown_A	373924938	373036968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067020	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067020	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067020	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	45026190	0	0
T1	373682	83434	0	0
T2	49862	15901	0	0
T3	44561	2624	0	0
T4	23838	1954	0	0
T11	426297	530696	0	0
T12	3995	704	0	0
T17	1966	407	0	0
T18	1411	264	0	0
T19	85385	12716	0	0
T20	1510	388	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	110891927	0	0
T1	373682	142258	0	0
T2	49862	13806	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067020	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067020	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	110891927	0	0
T1	373682	142258	0	0
T2	49862	13806	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373924938	373036968	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	373924938	105067063	0	0
GntImpliesValid_A	373924938	105067063	0	0
GrantKnown_A	373924938	373036968	0	0
IdxKnown_A	373924938	373036968	0	0
IndexIsCorrect_A	373924938	105067063	0	0
NoReadyValidNoGrant_A	373924938	45026177	0	0
Priority_A	373924938	110891983	0	0
ReadyAndValidImplyGrant_A	373924938	105067063	0	0
ReqAndReadyImplyGrant_A	373924938	105067063	0	0
ReqImpliesValid_A	373924938	110891983	0	0
ValidKnown_A	373924938	373036968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067063	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067063	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067063	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	45026177	0	0
T1	373682	83434	0	0
T2	49862	15901	0	0
T3	44561	2624	0	0
T4	23838	1954	0	0
T11	426297	530696	0	0
T12	3995	704	0	0
T17	1966	407	0	0
T18	1411	264	0	0
T19	85385	12716	0	0
T20	1510	388	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	110891983	0	0
T1	373682	142258	0	0
T2	49862	13806	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067063	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105067063	0	0
T1	373682	125651	0	0
T2	49862	10908	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	110891983	0	0
T1	373682	142258	0	0
T2	49862	13806	0	0
T3	44561	1316	0	0
T4	23838	1504	0	0
T11	426297	129432	0	0
T12	3995	182	0	0
T17	1966	419	0	0
T18	1411	66	0	0
T19	85385	52600	0	0
T20	1510	181	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T11

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373924938	373036968	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	373924938	99143016	0	0
GntImpliesValid_A	373924938	99143016	0	0
GrantKnown_A	373924938	373036968	0	0
IdxKnown_A	373924938	373036968	0	0
IndexIsCorrect_A	373924938	99143016	0	0
NoReadyValidNoGrant_A	373924938	42797420	0	0
Priority_A	373924938	105081756	0	0
ReadyAndValidImplyGrant_A	373924938	99143016	0	0
ReqAndReadyImplyGrant_A	373924938	99143016	0	0
ReqImpliesValid_A	373924938	105081756	0	0
ValidKnown_A	373924938	373036968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	42797420	0	0
T1	373682	73772	0	0
T2	49862	19324	0	0
T3	44561	0	0	0
T4	23838	53	0	0
T5	0	1806	0	0
T7	0	288232	0	0
T11	426297	524288	0	0
T12	3995	0	0	0
T15	0	524288	0	0
T17	1966	16	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	43	0	0
T58	0	790	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105081756	0	0
T1	373682	113802	0	0
T2	49862	13072	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105081756	0	0
T1	373682	113802	0	0
T2	49862	13072	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T11

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373924938	373036968	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	373924938	99143016	0	0
GntImpliesValid_A	373924938	99143016	0	0
GrantKnown_A	373924938	373036968	0	0
IdxKnown_A	373924938	373036968	0	0
IndexIsCorrect_A	373924938	99143016	0	0
NoReadyValidNoGrant_A	373924938	42797420	0	0
Priority_A	373924938	105081756	0	0
ReadyAndValidImplyGrant_A	373924938	99143016	0	0
ReqAndReadyImplyGrant_A	373924938	99143016	0	0
ReqImpliesValid_A	373924938	105081756	0	0
ValidKnown_A	373924938	373036968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	42797420	0	0
T1	373682	73772	0	0
T2	49862	19324	0	0
T3	44561	0	0	0
T4	23838	53	0	0
T5	0	1806	0	0
T7	0	288232	0	0
T11	426297	524288	0	0
T12	3995	0	0	0
T15	0	524288	0	0
T17	1966	16	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	43	0	0
T58	0	790	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105081756	0	0
T1	373682	113802	0	0
T2	49862	13072	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	99143016	0	0
T1	373682	104304	0	0
T2	49862	10879	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	105081756	0	0
T1	373682	113802	0	0
T2	49862	13072	0	0
T3	44561	0	0	0
T4	23838	1310	0	0
T5	0	30708	0	0
T6	0	14327	0	0
T11	426297	127897	0	0
T12	3995	0	0	0
T15	0	127897	0	0
T17	1966	4	0	0
T18	1411	0	0	0
T19	85385	0	0	0
T20	1510	16	0	0
T58	0	79695	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373924938	373036968	0	0
T1	373682	373586	0	0
T2	49862	49787	0	0
T3	44561	44492	0	0
T4	23838	22750	0	0
T11	426297	426281	0	0
T12	3995	3254	0	0
T17	1966	1791	0	0
T18	1411	1209	0	0
T19	85385	80214	0	0
T20	1510	1322	0	0