Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25109682 1 T1 83624 T2 65 T3 434
full_word 7961026 1 T1 13335 T2 42 T3 133


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 33070418 1 T1 96959 T2 107 T3 567
auto[TlIntgErrCmd] 80 1 T71 5 T230 7 T231 2
auto[TlIntgErrData] 113 1 T71 3 T230 8 T231 3
auto[TlIntgErrBoth] 97 1 T71 2 T230 5 T231 5


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28456632 1 T1 86965 T2 60 T3 477
auto[1] 4614076 1 T1 9994 T2 47 T3 90


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 24302033 1 T1 82363 T2 59 T3 422
auto[TlIntgErrNone] partial auto[1] 807378 1 T1 1261 T2 6 T3 12
auto[TlIntgErrNone] full_word auto[0] 4154453 1 T1 4602 T2 1 T3 55
auto[TlIntgErrNone] full_word auto[1] 3806554 1 T1 8733 T2 41 T3 78
auto[TlIntgErrCmd] partial auto[0] 31 1 T71 2 T230 2 T231 1
auto[TlIntgErrCmd] partial auto[1] 40 1 T71 2 T230 4 T231 1
auto[TlIntgErrCmd] full_word auto[0] 6 1 T230 1 T244 1 T289 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T71 1 T367 1 T365 1
auto[TlIntgErrData] partial auto[0] 57 1 T71 2 T230 3 T231 3
auto[TlIntgErrData] partial auto[1] 49 1 T71 1 T230 5 T244 1
auto[TlIntgErrData] full_word auto[0] 4 1 T273 1 T282 1 T368 1
auto[TlIntgErrData] full_word auto[1] 3 1 T289 2 T280 1 - -
auto[TlIntgErrBoth] partial auto[0] 46 1 T71 1 T230 2 T231 2
auto[TlIntgErrBoth] partial auto[1] 48 1 T71 1 T230 3 T231 3
auto[TlIntgErrBoth] full_word auto[0] 2 1 T273 1 T288 1 - -
auto[TlIntgErrBoth] full_word auto[1] 1 1 T367 1 - - - -


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 18532 1 T71 8 T201 304 T202 104
full_word 4164681 1 T3 10 T7 15741 T8 16993


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4182941 1 T3 10 T7 15741 T8 16993
auto[TlIntgErrCmd] 80 1 T71 3 T230 2 T231 2
auto[TlIntgErrData] 109 1 T230 8 T231 6 T244 3
auto[TlIntgErrBoth] 83 1 T71 5 T230 6 T231 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4160075 1 T3 10 T7 15741 T8 16993
auto[1] 23138 1 T71 3 T201 357 T202 123


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1091 1 T201 13 T202 7 T229 10
auto[TlIntgErrNone] partial auto[1] 17192 1 T201 291 T202 97 T229 72
auto[TlIntgErrNone] full_word auto[0] 4158867 1 T3 10 T7 15741 T8 16993
auto[TlIntgErrNone] full_word auto[1] 5791 1 T201 66 T202 26 T229 24
auto[TlIntgErrCmd] partial auto[0] 25 1 T71 1 T231 1 T244 2
auto[TlIntgErrCmd] partial auto[1] 45 1 T71 2 T230 2 T244 2
auto[TlIntgErrCmd] full_word auto[0] 1 1 T366 1 - - - -
auto[TlIntgErrCmd] full_word auto[1] 9 1 T231 1 T285 1 T273 1
auto[TlIntgErrData] partial auto[0] 53 1 T230 8 T231 5 T244 2
auto[TlIntgErrData] partial auto[1] 49 1 T231 1 T244 1 T243 2
auto[TlIntgErrData] full_word auto[0] 1 1 T280 1 - - - -
auto[TlIntgErrData] full_word auto[1] 6 1 T280 1 T282 2 T367 1
auto[TlIntgErrBoth] partial auto[0] 33 1 T71 4 T230 6 T244 1
auto[TlIntgErrBoth] partial auto[1] 44 1 T71 1 T231 2 T244 2
auto[TlIntgErrBoth] full_word auto[0] 4 1 T289 1 T280 1 T292 1
auto[TlIntgErrBoth] full_word auto[1] 2 1 T282 1 T369 1 - -

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%