Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1589740924	1586547292	0	0
CheckNGreaterZero_A	4116	4116	0	0
GntImpliesReady_A	1589740924	397399535	0	0
GntImpliesValid_A	1589740924	397399535	0	0
GrantKnown_A	1589740924	1586547292	0	0
IdxKnown_A	1589740924	1586547292	0	0
IndexIsCorrect_A	1589740924	397399535	0	0
NoReadyValidNoGrant_A	1589740924	174347737	0	0
Priority_A	1589740924	421470806	0	0
ReadyAndValidImplyGrant_A	1589740924	397399535	0	0
ReqAndReadyImplyGrant_A	1589740924	397399535	0	0
ReqImpliesValid_A	1589740924	421470806	0	0
ValidKnown_A	1589740924	1586547292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	1586547292	0	0
T1	872044	820868	0	0
T2	4376	3556	0	0
T3	12072	11432	0	0
T4	391204	390840	0	0
T7	262592	262304	0	0
T8	493960	493656	0	0
T13	12604	9792	0	0
T14	4044	3780	0	0
T19	11492	11220	0	0
T20	34372	33760	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4116	4116	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	397399535	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	45064	0	0
T8	493960	156704	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	397399535	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	45064	0	0
T8	493960	156704	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	1586547292	0	0
T1	872044	820868	0	0
T2	4376	3556	0	0
T3	12072	11432	0	0
T4	391204	390840	0	0
T7	262592	262304	0	0
T8	493960	493656	0	0
T13	12604	9792	0	0
T14	4044	3780	0	0
T19	11492	11220	0	0
T20	34372	33760	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	1586547292	0	0
T1	872044	820868	0	0
T2	4376	3556	0	0
T3	12072	11432	0	0
T4	391204	390840	0	0
T7	262592	262304	0	0
T8	493960	493656	0	0
T13	12604	9792	0	0
T14	4044	3780	0	0
T19	11492	11220	0	0
T20	34372	33760	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	397399535	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	45064	0	0
T8	493960	156704	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	174347737	0	0
T1	436022	64448	0	0
T2	2188	528	0	0
T3	12072	850	0	0
T4	391204	7480	0	0
T5	0	82	0	0
T7	262592	129292	0	0
T8	493960	72240	0	0
T13	12604	592	0	0
T14	4044	292	0	0
T16	0	2450	0	0
T19	11492	256	0	0
T20	34372	1600	0	0
T31	0	300	0	0
T32	3678	60	0	0
T47	963466	0	0	0
T48	0	52	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	421470806	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	48668	0	0
T8	493960	189358	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	397399535	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	45064	0	0
T8	493960	156704	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	397399535	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	45064	0	0
T8	493960	156704	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	421470806	0	0
T1	436022	271136	0	0
T2	2188	132	0	0
T3	12072	814	0	0
T4	391204	122896	0	0
T5	0	28	0	0
T6	0	446	0	0
T7	262592	48668	0	0
T8	493960	189358	0	0
T13	12604	148	0	0
T14	4044	76	0	0
T19	11492	64	0	0
T20	34372	11028	0	0
T31	0	3246	0	0
T32	3678	34	0	0
T47	963466	0	0	0
T48	0	358	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589740924	1586547292	0	0
T1	872044	820868	0	0
T2	4376	3556	0	0
T3	12072	11432	0	0
T4	391204	390840	0	0
T7	262592	262304	0	0
T8	493960	493656	0	0
T13	12604	9792	0	0
T14	4044	3780	0	0
T19	11492	11220	0	0
T20	34372	33760	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397435231	396636823	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	397435231	101074930	0	0
GntImpliesValid_A	397435231	101074930	0	0
GrantKnown_A	397435231	396636823	0	0
IdxKnown_A	397435231	396636823	0	0
IndexIsCorrect_A	397435231	101074930	0	0
NoReadyValidNoGrant_A	397435231	44509981	0	0
Priority_A	397435231	107215762	0	0
ReadyAndValidImplyGrant_A	397435231	101074930	0	0
ReqAndReadyImplyGrant_A	397435231	101074930	0	0
ReqImpliesValid_A	397435231	107215762	0	0
ValidKnown_A	397435231	396636823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101074930	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101074930	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101074930	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	44509981	0	0
T1	218011	32224	0	0
T2	1094	264	0	0
T3	3018	390	0	0
T4	97801	1778	0	0
T7	65648	30430	0	0
T8	123490	12412	0	0
T13	3151	296	0	0
T14	1011	146	0	0
T19	2873	128	0	0
T20	8593	666	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	107215762	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	11556	0	0
T8	123490	22000	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101074930	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101074930	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	107215762	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	11556	0	0
T8	123490	22000	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397435231	396636823	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	397435231	101075004	0	0
GntImpliesValid_A	397435231	101075004	0	0
GrantKnown_A	397435231	396636823	0	0
IdxKnown_A	397435231	396636823	0	0
IndexIsCorrect_A	397435231	101075004	0	0
NoReadyValidNoGrant_A	397435231	44509972	0	0
Priority_A	397435231	107215845	0	0
ReadyAndValidImplyGrant_A	397435231	101075004	0	0
ReqAndReadyImplyGrant_A	397435231	101075004	0	0
ReqImpliesValid_A	397435231	107215845	0	0
ValidKnown_A	397435231	396636823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101075004	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101075004	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101075004	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	44509972	0	0
T1	218011	32224	0	0
T2	1094	264	0	0
T3	3018	390	0	0
T4	97801	1778	0	0
T7	65648	30430	0	0
T8	123490	12412	0	0
T13	3151	296	0	0
T14	1011	146	0	0
T19	2873	128	0	0
T20	8593	666	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	107215845	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	11556	0	0
T8	123490	22000	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101075004	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	101075004	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	10570	0	0
T8	123490	19179	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	107215845	0	0
T1	218011	135568	0	0
T2	1094	66	0	0
T3	3018	114	0	0
T4	97801	27907	0	0
T7	65648	11556	0	0
T8	123490	22000	0	0
T13	3151	74	0	0
T14	1011	38	0	0
T19	2873	32	0	0
T20	8593	5198	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T4,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397435231	396636823	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	397435231	97624868	0	0
GntImpliesValid_A	397435231	97624868	0	0
GrantKnown_A	397435231	396636823	0	0
IdxKnown_A	397435231	396636823	0	0
IndexIsCorrect_A	397435231	97624868	0	0
NoReadyValidNoGrant_A	397435231	42663892	0	0
Priority_A	397435231	103519667	0	0
ReadyAndValidImplyGrant_A	397435231	97624868	0	0
ReqAndReadyImplyGrant_A	397435231	97624868	0	0
ReqImpliesValid_A	397435231	103519667	0	0
ValidKnown_A	397435231	396636823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624868	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624868	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624868	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	42663892	0	0
T3	3018	35	0	0
T4	97801	1962	0	0
T5	0	41	0	0
T7	65648	34216	0	0
T8	123490	23708	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T16	0	1225	0	0
T19	2873	0	0	0
T20	8593	134	0	0
T31	0	150	0	0
T32	1839	30	0	0
T47	481733	0	0	0
T48	0	26	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	103519667	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	12778	0	0
T8	123490	72679	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624868	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624868	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	103519667	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	12778	0	0
T8	123490	72679	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T4,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397435231	396636823	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	397435231	97624733	0	0
GntImpliesValid_A	397435231	97624733	0	0
GrantKnown_A	397435231	396636823	0	0
IdxKnown_A	397435231	396636823	0	0
IndexIsCorrect_A	397435231	97624733	0	0
NoReadyValidNoGrant_A	397435231	42663892	0	0
Priority_A	397435231	103519532	0	0
ReadyAndValidImplyGrant_A	397435231	97624733	0	0
ReqAndReadyImplyGrant_A	397435231	97624733	0	0
ReqImpliesValid_A	397435231	103519532	0	0
ValidKnown_A	397435231	396636823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624733	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624733	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624733	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	42663892	0	0
T3	3018	35	0	0
T4	97801	1962	0	0
T5	0	41	0	0
T7	65648	34216	0	0
T8	123490	23708	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T16	0	1225	0	0
T19	2873	0	0	0
T20	8593	134	0	0
T31	0	150	0	0
T32	1839	30	0	0
T47	481733	0	0	0
T48	0	26	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	103519532	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	12778	0	0
T8	123490	72679	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624733	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	97624733	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	11962	0	0
T8	123490	59173	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	103519532	0	0
T3	3018	293	0	0
T4	97801	33541	0	0
T5	0	14	0	0
T6	0	223	0	0
T7	65648	12778	0	0
T8	123490	72679	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	316	0	0
T31	0	1623	0	0
T32	1839	17	0	0
T47	481733	0	0	0
T48	0	179	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0