Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23429148	1		T1	57		T2	1242		T3	153
full_word	7839961	1		T1	1		T2	483		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31268819	1		T1	58		T2	1725		T3	155
auto[TlIntgErrCmd]	83	1		T62	5		T212	6		T247	7
auto[TlIntgErrData]	99	1		T62	2		T212	8		T247	6
auto[TlIntgErrBoth]	108	1		T62	3		T212	6		T247	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26743998	1		T1	57		T2	1459		T3	146
auto[1]	4525111	1		T1	1		T2	266		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22630757	1		T1	57		T2	1180		T3	145
auto[TlIntgErrNone]	partial	auto[1]	798122	1		T2	62		T3	8		T4	2821
auto[TlIntgErrNone]	full_word	auto[0]	4113104	1		T2	279		T3	1		T4	10133
auto[TlIntgErrNone]	full_word	auto[1]	3726836	1		T1	1		T2	204		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T62	3		T212	2		T247	4
auto[TlIntgErrCmd]	partial	auto[1]	41	1		T62	2		T212	3		T247	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T212	1		T348	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T341	2		T342	1		T259	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T62	1		T212	6		T247	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T62	1		T212	2		T247	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T247	1		T266	1		T342	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T348	1		T344	1		T342	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1		T62	2		T212	3		T247	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T62	1		T212	3		T247	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T349	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T343	1		T265	1		T259	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19278	1		T62	10		T185	60		T186	56
full_word	4021239	1		T2	8		T4	37411		T5	16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4040246	1		T2	8		T4	37411		T5	16
auto[TlIntgErrCmd]	93	1		T62	3		T212	10		T247	4
auto[TlIntgErrData]	98	1		T62	3		T212	7		T247	8
auto[TlIntgErrBoth]	80	1		T62	4		T212	3		T247	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4016453	1		T2	8		T4	37411		T5	16
auto[1]	24064	1		T62	6		T185	79		T186	85

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1111	1		T185	4		T186	1		T211	18
auto[TlIntgErrNone]	partial	auto[1]	17919	1		T185	56		T186	55		T211	399
auto[TlIntgErrNone]	full_word	auto[0]	4015231	1		T2	8		T4	37411		T5	16
auto[TlIntgErrNone]	full_word	auto[1]	5985	1		T185	23		T186	30		T211	191
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T62	1		T212	4		T247	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T62	2		T212	5		T247	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T341	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T212	1		T265	1		T259	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T62	2		T212	3		T247	3
auto[TlIntgErrData]	partial	auto[1]	46	1		T62	1		T212	4		T247	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T262	2		T342	1		T340	2
auto[TlIntgErrData]	full_word	auto[1]	2	1		T349	1		T347	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T62	1		T247	3		T341	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T62	3		T212	3		T247	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T344	1		T345	1		T347	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T247	1		T341	1		T344	1