Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
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Group Instance : mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 91 1 T7 2 T30 2 T174 2
others[1] 73 1 T7 2 T29 1 T30 1
others[2] 85 1 T7 1 T29 4 T30 1
others[3] 140 1 T7 5 T29 1 T30 2
false 25459 1 T1 1 T3 10 T4 1
true 20672 1 T2 3 T4 1 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 4 1 T184 1 T182 1 T350 1
others[1] 4 1 T99 1 T351 1 T352 1
others[2] 5 1 T98 1 T40 1 T353 1
others[3] 6 1 T183 1 T354 1 T355 1
false 11430 1 T1 1 T2 2 T3 10
true 4 1 T167 1 T356 1 T357 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2131 1 T20 20 T29 1 T30 2
others[1] 2207 1 T20 34 T30 1 T75 71
others[2] 2218 1 T7 1 T20 24 T29 1
others[3] 3605 1 T20 37 T30 2 T75 96
false 6841 1 T1 1 T3 10 T4 1
true 1503 1 T2 3 T4 1 T5 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2114 1 T7 1 T20 22 T29 1
others[1] 2147 1 T7 1 T20 19 T29 2
others[2] 2077 1 T7 1 T20 28 T29 1
others[3] 3794 1 T7 4 T20 46 T29 1
false 6866 1 T1 1 T3 10 T4 1
true 1504 1 T2 3 T4 1 T5 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2185 1 T20 31 T75 57 T44 38
others[1] 2028 1 T20 18 T52 1 T75 58
others[2] 2143 1 T20 29 T75 49 T44 57
others[3] 3616 1 T20 37 T75 95 T44 64
false 7302 1 T1 1 T2 2 T3 10
true 40 1 T1 1 T358 1 T359 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 69 1 T30 1 T174 1 T200 1
others[1] 79 1 T7 2 T29 3 T30 3
others[2] 82 1 T7 1 T29 1 T30 1
others[3] 141 1 T7 4 T29 3 T30 3
false 25371 1 T1 1 T3 10 T4 1
true 20715 1 T2 3 T4 1 T5 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 7088 1 T20 83 T75 162 T44 129
others[1] 7161 1 T20 90 T75 204 T44 141
others[2] 6936 1 T20 71 T75 181 T44 143
others[3] 11702 1 T20 137 T75 285 T44 237
false 3474 1 T20 45 T75 82 T44 61
true 17805 1 T1 1 T2 2 T3 10

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