Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1602054332	1598959564	0	0
CheckNGreaterZero_A	4112	4112	0	0
GntImpliesReady_A	1602054332	398515976	0	0
GntImpliesValid_A	1602054332	398515976	0	0
GrantKnown_A	1602054332	1598959564	0	0
IdxKnown_A	1602054332	1598959564	0	0
IndexIsCorrect_A	1602054332	398515976	0	0
NoReadyValidNoGrant_A	1602054332	185385996	0	0
Priority_A	1602054332	421848492	0	0
ReadyAndValidImplyGrant_A	1602054332	398515976	0	0
ReqAndReadyImplyGrant_A	1602054332	398515976	0	0
ReqImpliesValid_A	1602054332	421848492	0	0
ValidKnown_A	1602054332	1598959564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	1598959564	0	0
T1	4372	4076	0	0
T2	18344	17784	0	0
T3	13936	11156	0	0
T4	1528656	1528268	0	0
T5	2212	1936	0	0
T6	13540	13296	0	0
T7	702468	702252	0	0
T9	16952	15052	0	0
T19	3575984	3575424	0	0
T20	522092	498776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4112	4112	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T9	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	398515976	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	458420	0	0
T5	2212	130	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	20482	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	235014	0	0
T52	2594	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	398515976	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	458420	0	0
T5	2212	130	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	20482	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	235014	0	0
T52	2594	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	1598959564	0	0
T1	4372	4076	0	0
T2	18344	17784	0	0
T3	13936	11156	0	0
T4	1528656	1528268	0	0
T5	2212	1936	0	0
T6	13540	13296	0	0
T7	702468	702252	0	0
T9	16952	15052	0	0
T19	3575984	3575424	0	0
T20	522092	498776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	1598959564	0	0
T1	4372	4076	0	0
T2	18344	17784	0	0
T3	13936	11156	0	0
T4	1528656	1528268	0	0
T5	2212	1936	0	0
T6	13540	13296	0	0
T7	702468	702252	0	0
T9	16952	15052	0	0
T19	3575984	3575424	0	0
T20	522092	498776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	398515976	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	458420	0	0
T5	2212	130	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	20482	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	235014	0	0
T52	2594	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	185385996	0	0
T1	2186	256	0	0
T2	18344	1654	0	0
T3	13936	1188	0	0
T4	1528656	336788	0	0
T5	2212	406	0	0
T6	13540	286	0	0
T7	702468	128	0	0
T8	0	25344	0	0
T9	16952	1536	0	0
T16	0	3978	0	0
T19	3575984	352	0	0
T20	522092	28520	0	0
T22	0	1258	0	0
T24	0	100	0	0
T37	0	150280	0	0
T38	0	160418	0	0
T52	2594	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	421848492	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	525450	0	0
T5	2212	144	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	26816	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	261652	0	0
T52	2594	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	398515976	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	458420	0	0
T5	2212	130	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	20482	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	235014	0	0
T52	2594	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	398515976	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	458420	0	0
T5	2212	130	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	20482	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	235014	0	0
T52	2594	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	421848492	0	0
T1	2186	64	0	0
T2	18344	2708	0	0
T3	13936	298	0	0
T4	1528656	525450	0	0
T5	2212	144	0	0
T6	13540	922	0	0
T7	702468	26644	0	0
T8	0	26816	0	0
T9	16952	436	0	0
T19	3575984	1378	0	0
T20	522092	114300	0	0
T22	0	838	0	0
T23	0	175616	0	0
T24	0	34	0	0
T37	0	261652	0	0
T52	2594	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602054332	1598959564	0	0
T1	4372	4076	0	0
T2	18344	17784	0	0
T3	13936	11156	0	0
T4	1528656	1528268	0	0
T5	2212	1936	0	0
T6	13540	13296	0	0
T7	702468	702252	0	0
T9	16952	15052	0	0
T19	3575984	3575424	0	0
T20	522092	498776	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400513583	399739891	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	400513583	103024881	0	0
GntImpliesValid_A	400513583	103024881	0	0
GrantKnown_A	400513583	399739891	0	0
IdxKnown_A	400513583	399739891	0	0
IndexIsCorrect_A	400513583	103024881	0	0
NoReadyValidNoGrant_A	400513583	47432304	0	0
Priority_A	400513583	108885381	0	0
ReadyAndValidImplyGrant_A	400513583	103024881	0	0
ReqAndReadyImplyGrant_A	400513583	103024881	0	0
ReqImpliesValid_A	400513583	108885381	0	0
ValidKnown_A	400513583	399739891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024881	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024881	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024881	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	47432304	0	0
T1	1093	128	0	0
T2	4586	610	0	0
T3	3484	594	0	0
T4	382164	89405	0	0
T5	553	141	0	0
T6	3385	128	0	0
T7	175617	64	0	0
T9	4238	768	0	0
T19	893996	176	0	0
T20	130523	14260	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	108885381	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	114877	0	0
T5	553	43	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024881	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024881	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	108885381	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	114877	0	0
T5	553	43	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400513583	399739891	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	400513583	103024621	0	0
GntImpliesValid_A	400513583	103024621	0	0
GrantKnown_A	400513583	399739891	0	0
IdxKnown_A	400513583	399739891	0	0
IndexIsCorrect_A	400513583	103024621	0	0
NoReadyValidNoGrant_A	400513583	47432304	0	0
Priority_A	400513583	108885121	0	0
ReadyAndValidImplyGrant_A	400513583	103024621	0	0
ReqAndReadyImplyGrant_A	400513583	103024621	0	0
ReqImpliesValid_A	400513583	108885121	0	0
ValidKnown_A	400513583	399739891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024621	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024621	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024621	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	47432304	0	0
T1	1093	128	0	0
T2	4586	610	0	0
T3	3484	594	0	0
T4	382164	89405	0	0
T5	553	141	0	0
T6	3385	128	0	0
T7	175617	64	0	0
T9	4238	768	0	0
T19	893996	176	0	0
T20	130523	14260	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	108885121	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	114877	0	0
T5	553	43	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024621	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	103024621	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	96537	0	0
T5	553	40	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	108885121	0	0
T1	1093	32	0	0
T2	4586	1263	0	0
T3	3484	149	0	0
T4	382164	114877	0	0
T5	553	43	0	0
T6	3385	93	0	0
T7	175617	13322	0	0
T9	4238	208	0	0
T19	893996	689	0	0
T20	130523	57150	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400513583	399739891	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	400513583	96233237	0	0
GntImpliesValid_A	400513583	96233237	0	0
GrantKnown_A	400513583	399739891	0	0
IdxKnown_A	400513583	399739891	0	0
IndexIsCorrect_A	400513583	96233237	0	0
NoReadyValidNoGrant_A	400513583	45260694	0	0
Priority_A	400513583	102038995	0	0
ReadyAndValidImplyGrant_A	400513583	96233237	0	0
ReqAndReadyImplyGrant_A	400513583	96233237	0	0
ReqImpliesValid_A	400513583	102038995	0	0
ValidKnown_A	400513583	399739891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	45260694	0	0
T2	4586	217	0	0
T3	3484	0	0	0
T4	382164	78989	0	0
T5	553	62	0	0
T6	3385	15	0	0
T7	175617	0	0	0
T8	0	12672	0	0
T9	4238	0	0	0
T16	0	1989	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	629	0	0
T24	0	50	0	0
T37	0	75140	0	0
T38	0	80209	0	0
T52	1297	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	102038995	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	147848	0	0
T5	553	29	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	13408	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	130826	0	0
T52	1297	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	102038995	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	147848	0	0
T5	553	29	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	13408	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	130826	0	0
T52	1297	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400513583	399739891	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	400513583	96233237	0	0
GntImpliesValid_A	400513583	96233237	0	0
GrantKnown_A	400513583	399739891	0	0
IdxKnown_A	400513583	399739891	0	0
IndexIsCorrect_A	400513583	96233237	0	0
NoReadyValidNoGrant_A	400513583	45260694	0	0
Priority_A	400513583	102038995	0	0
ReadyAndValidImplyGrant_A	400513583	96233237	0	0
ReqAndReadyImplyGrant_A	400513583	96233237	0	0
ReqImpliesValid_A	400513583	102038995	0	0
ValidKnown_A	400513583	399739891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	45260694	0	0
T2	4586	217	0	0
T3	3484	0	0	0
T4	382164	78989	0	0
T5	553	62	0	0
T6	3385	15	0	0
T7	175617	0	0	0
T8	0	12672	0	0
T9	4238	0	0	0
T16	0	1989	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	629	0	0
T24	0	50	0	0
T37	0	75140	0	0
T38	0	80209	0	0
T52	1297	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	102038995	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	147848	0	0
T5	553	29	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	13408	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	130826	0	0
T52	1297	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	96233237	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	132673	0	0
T5	553	25	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	10241	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	117507	0	0
T52	1297	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	102038995	0	0
T2	4586	91	0	0
T3	3484	0	0	0
T4	382164	147848	0	0
T5	553	29	0	0
T6	3385	368	0	0
T7	175617	0	0	0
T8	0	13408	0	0
T9	4238	10	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T22	0	419	0	0
T23	0	87808	0	0
T24	0	17	0	0
T37	0	130826	0	0
T52	1297	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0