Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T136,T125
1	0	Covered	T9,T136,T125

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T136,T125

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T136,T125
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T61,T56,T151

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T56,T152,T217

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T56,T152,T217

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T61,T56,T151

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T61,T56,T151

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T9,T7
1	Covered	T4,T5,T9

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T6,T19

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T19
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T6,T19

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T5,T9
StCalcMask	237	Covered	T4,T5,T9
StCalcPlainEcc	215	Covered	T4,T5,T6
StDisabled	193	Covered	T3,T9,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T6
StPostPack	218	Covered	T61,T56,T151
StPrePack	195	Covered	T56,T152,T217
StReqFlash	237	Covered	T4,T5,T6
StScrambleData	244	Covered	T4,T5,T9
StWaitFlash	270	Covered	T4,T6,T19

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T5,T9
StCalcMask->StScrambleData	244	Covered	T4,T5,T9
StCalcPlainEcc->StCalcMask	237	Covered	T4,T5,T9
StCalcPlainEcc->StReqFlash	237	Covered	T6,T9,T7
StIdle->StDisabled	193	Covered	T3,T9,T12
StIdle->StPackData	197	Covered	T4,T5,T6
StIdle->StPrePack	195	Covered	T56,T152,T217
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T6
StPackData->StPostPack	218	Covered	T61,T56,T151
StPostPack->StCalcPlainEcc	231	Covered	T61,T56,T151
StPrePack->StPackData	205	Covered	T56,T152,T217
StReqFlash->StIdle	273	Covered	T4,T5,T6
StReqFlash->StWaitFlash	270	Covered	T4,T6,T19
StScrambleData->StCalcEcc	252	Covered	T4,T5,T9
StWaitFlash->StIdle	280	Covered	T4,T6,T19

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T19
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T217
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T217
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T61,T56,T151
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T61,T56,T151
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T9
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T9,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T5,T9
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T5,T9
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T9
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T9
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T6,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T6,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T6,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T19
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T19
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T6
0	0	1	-	-	Covered	T4,T5,T9
0	0	0	1	-	Covered	T4,T5,T9
0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	801027166	2431589	0	0
PostPackRule_A	801027166	1919	0	0
PrePackRule_A	801027166	1325	0	0
WidthCheck_A	2056	2056	0	0
u_state_regs_A	801027166	799479782	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801027166	2431589	0	0
T4	764328	1596	0	0
T5	1106	0	0	0
T6	6770	3	0	0
T7	351234	32	0	0
T9	8476	0	0	0
T12	8584	0	0	0
T15	2534	0	0	0
T19	1787992	3	0	0
T20	261046	119	0	0
T23	0	1291	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	0	885	0	0
T28	0	494	0	0
T30	0	64	0	0
T37	0	1724	0	0
T38	0	682	0	0
T52	2594	0	0	0
T55	0	566	0	0
T56	0	32777	0	0
T75	0	240	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801027166	1919	0	0
T25	6070	0	0	0
T26	5332	0	0	0
T35	322954	0	0	0
T56	280218	7	0	0
T61	1750	1	0	0
T65	139628	0	0	0
T66	0	55	0	0
T73	818	0	0	0
T80	0	7	0	0
T81	0	7	0	0
T91	0	10	0	0
T94	0	1	0	0
T103	0	5	0	0
T136	782964	0	0	0
T151	3572	1	0	0
T152	0	2	0	0
T170	0	32	0	0
T173	1548	0	0	0
T201	3176	0	0	0
T217	0	3	0	0
T218	3164	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801027166	1325	0	0
T25	6070	0	0	0
T26	5332	0	0	0
T35	322954	0	0	0
T56	280218	7	0	0
T65	279256	0	0	0
T66	0	31	0	0
T73	1636	0	0	0
T80	0	7	0	0
T81	0	5	0	0
T91	0	5	0	0
T103	0	2	0	0
T108	0	7	0	0
T136	782964	0	0	0
T151	3572	0	0	0
T152	0	2	0	0
T168	0	18	0	0
T170	0	15	0	0
T171	0	18	0	0
T201	3176	0	0	0
T217	0	1	0	0
T218	3164	0	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2056	2056	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T9	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801027166	799479782	0	0
T1	2186	2038	0	0
T2	9172	8892	0	0
T3	6968	5578	0	0
T4	764328	764134	0	0
T5	1106	968	0	0
T6	6770	6648	0	0
T7	351234	351126	0	0
T9	8476	7526	0	0
T19	1787992	1787712	0	0
T20	261046	249388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T136,T125
1	0	Covered	T9,T136,T125

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T9
1	1	Covered	T9,T136,T125

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T136,T125
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T6,T9
1	Covered	T61,T56,T151

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9
1	1	Covered	T4,T6,T9

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T9
1	1	Covered	T56,T152,T170

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T56,T152,T170

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9
1	1	Covered	T4,T6,T9

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T6,T9
1	Covered	T4,T6,T9

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T6,T9
1	1	Covered	T61,T56,T151

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T61,T56,T151

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T9,T7
1	Covered	T4,T9,T19

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T7,T20
1	Covered	T4,T6,T19

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T7,T20
1	Covered	T4,T9,T19

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T20
1	1	Covered	T4,T6,T19

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T19
1	1	Covered	T4,T9,T19

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T19
1	1	Covered	T4,T9,T19

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T19
1	1	0	Covered	T4,T6,T9
1	1	1	Covered	T4,T6,T19

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T19

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T9,T19
StCalcMask	237	Covered	T4,T9,T19
StCalcPlainEcc	215	Covered	T4,T6,T9
StDisabled	193	Covered	T3,T9,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T6,T9
StPostPack	218	Covered	T61,T56,T151
StPrePack	195	Covered	T56,T152,T170
StReqFlash	237	Covered	T4,T6,T9
StScrambleData	244	Covered	T4,T9,T19
StWaitFlash	270	Covered	T4,T6,T19

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T9,T19
StCalcMask->StScrambleData	244	Covered	T4,T9,T19
StCalcPlainEcc->StCalcMask	237	Covered	T4,T9,T19
StCalcPlainEcc->StReqFlash	237	Covered	T6,T9,T7
StIdle->StDisabled	193	Covered	T3,T9,T12
StIdle->StPackData	197	Covered	T4,T6,T9
StIdle->StPrePack	195	Covered	T56,T152,T170
StPackData->StCalcPlainEcc	215	Covered	T4,T6,T9
StPackData->StPostPack	218	Covered	T61,T56,T151
StPostPack->StCalcPlainEcc	231	Covered	T61,T56,T151
StPrePack->StPackData	205	Covered	T56,T152,T170
StReqFlash->StIdle	273	Covered	T4,T9,T19
StReqFlash->StWaitFlash	270	Covered	T4,T6,T19
StScrambleData->StCalcEcc	252	Covered	T4,T9,T19
StWaitFlash->StIdle	280	Covered	T4,T6,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T19
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T9
0	0	1	Covered	T4,T6,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T170
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T170
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T61,T56,T151
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T9
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T61,T56,T151
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T9,T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T9,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T9,T19
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T9,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T9,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T9,T19
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T6,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T7,T20
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T9,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T7,T20
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T19
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T19
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T6,T19
0	0	1	-	-	Covered	T4,T9,T19
0	0	0	1	-	Covered	T4,T9,T19
0	0	0	0	1	Covered	T4,T6,T9
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	400513583	1218279	0	0
PostPackRule_A	400513583	947	0	0
PrePackRule_A	400513583	633	0	0
WidthCheck_A	1028	1028	0	0
u_state_regs_A	400513583	399739891	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	1218279	0	0
T4	382164	750	0	0
T5	553	0	0	0
T6	3385	1	0	0
T7	175617	32	0	0
T9	4238	0	0	0
T12	4292	0	0	0
T15	1267	0	0	0
T19	893996	3	0	0
T20	130523	119	0	0
T23	0	652	0	0
T24	0	2	0	0
T30	0	64	0	0
T37	0	976	0	0
T52	1297	0	0	0
T75	0	240	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	947	0	0
T25	3035	0	0	0
T26	2666	0	0	0
T35	161477	0	0	0
T56	140109	2	0	0
T61	1750	1	0	0
T66	0	25	0	0
T80	0	5	0	0
T81	0	1	0	0
T91	0	5	0	0
T103	0	2	0	0
T136	391482	0	0	0
T151	1786	1	0	0
T152	0	1	0	0
T170	0	16	0	0
T173	1548	0	0	0
T201	1588	0	0	0
T218	1582	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	633	0	0
T25	3035	0	0	0
T26	2666	0	0	0
T35	161477	0	0	0
T56	140109	1	0	0
T65	139628	0	0	0
T66	0	11	0	0
T73	818	0	0	0
T80	0	5	0	0
T81	0	2	0	0
T91	0	2	0	0
T108	0	7	0	0
T136	391482	0	0	0
T151	1786	0	0	0
T152	0	1	0	0
T168	0	18	0	0
T170	0	9	0	0
T171	0	10	0	0
T201	1588	0	0	0
T218	1582	0	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11
1	0	Covered	T9,T11

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T11

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11
1	0	Covered	T2,T4,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T152,T217

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T56,T152,T217

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T56,T152,T217

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T56,T152,T217

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13,T14
1	Covered	T56,T152,T217

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T9,T23
1	Covered	T4,T5,T23

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T23
1	Covered	T4,T6,T23

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T23
1	Covered	T4,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T23
1	1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T37
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T23
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T6,T23

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T23

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T5,T23
StCalcMask	237	Covered	T4,T5,T23
StCalcPlainEcc	215	Covered	T4,T5,T6
StDisabled	193	Covered	T3,T9,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T6
StPostPack	218	Covered	T56,T152,T217
StPrePack	195	Covered	T56,T152,T217
StReqFlash	237	Covered	T4,T5,T6
StScrambleData	244	Covered	T4,T5,T23
StWaitFlash	270	Covered	T4,T6,T23

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T5,T23
StCalcMask->StScrambleData	244	Covered	T4,T5,T23
StCalcPlainEcc->StCalcMask	237	Covered	T4,T5,T23
StCalcPlainEcc->StReqFlash	237	Covered	T6,T9,T23
StIdle->StDisabled	193	Covered	T3,T9,T12
StIdle->StPackData	197	Covered	T4,T5,T6
StIdle->StPrePack	195	Covered	T56,T152,T217
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T6
StPackData->StPostPack	218	Covered	T56,T152,T217
StPostPack->StCalcPlainEcc	231	Covered	T56,T152,T217
StPrePack->StPackData	205	Covered	T56,T152,T217
StReqFlash->StIdle	273	Covered	T4,T5,T6
StReqFlash->StWaitFlash	270	Covered	T4,T6,T23
StScrambleData->StCalcEcc	252	Covered	T4,T5,T23
StWaitFlash->StIdle	280	Covered	T4,T6,T23

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T23
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T217
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T217
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T56,T152,T217
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T56,T152,T217
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T23
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T9,T23
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T5,T23
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T5,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T23
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T23
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T6,T23
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T6,T23
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T6,T23
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T23
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T23
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T6
0	0	1	-	-	Covered	T4,T5,T23
0	0	0	1	-	Covered	T4,T5,T23
0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	400513583	1213310	0	0
PostPackRule_A	400513583	972	0	0
PrePackRule_A	400513583	692	0	0
WidthCheck_A	1028	1028	0	0
u_state_regs_A	400513583	399739891	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	1213310	0	0
T4	382164	846	0	0
T5	553	0	0	0
T6	3385	2	0	0
T7	175617	0	0	0
T9	4238	0	0	0
T12	4292	0	0	0
T15	1267	0	0	0
T19	893996	0	0	0
T20	130523	0	0	0
T23	0	639	0	0
T25	0	1	0	0
T27	0	885	0	0
T28	0	494	0	0
T37	0	748	0	0
T38	0	682	0	0
T52	1297	0	0	0
T55	0	566	0	0
T56	0	32777	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	972	0	0
T25	3035	0	0	0
T26	2666	0	0	0
T35	161477	0	0	0
T56	140109	5	0	0
T65	139628	0	0	0
T66	0	30	0	0
T73	818	0	0	0
T80	0	2	0	0
T81	0	6	0	0
T91	0	5	0	0
T94	0	1	0	0
T103	0	3	0	0
T136	391482	0	0	0
T151	1786	0	0	0
T152	0	1	0	0
T170	0	16	0	0
T201	1588	0	0	0
T217	0	3	0	0
T218	1582	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	692	0	0
T25	3035	0	0	0
T26	2666	0	0	0
T35	161477	0	0	0
T56	140109	6	0	0
T65	139628	0	0	0
T66	0	20	0	0
T73	818	0	0	0
T80	0	2	0	0
T81	0	3	0	0
T91	0	3	0	0
T103	0	2	0	0
T136	391482	0	0	0
T151	1786	0	0	0
T152	0	1	0	0
T170	0	6	0	0
T171	0	8	0	0
T201	1588	0	0	0
T217	0	1	0	0
T218	1582	0	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400513583	399739891	0	0
T1	1093	1019	0	0
T2	4586	4446	0	0
T3	3484	2789	0	0
T4	382164	382067	0	0
T5	553	484	0	0
T6	3385	3324	0	0
T7	175617	175563	0	0
T9	4238	3763	0	0
T19	893996	893856	0	0
T20	130523	124694	0	0