Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23656092	1		T1	51940		T2	21		T3	122
full_word	7724876	1		T1	8300		T2	1		T3	57

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31380688	1		T1	60240		T2	22		T3	179
auto[TlIntgErrCmd]	97	1		T72	7		T74	4		T215	7
auto[TlIntgErrData]	84	1		T72	4		T74	5		T215	7
auto[TlIntgErrBoth]	99	1		T72	9		T74	1		T215	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26951924	1		T1	54081		T2	21		T3	58
auto[1]	4429044	1		T1	6159		T2	1		T3	121

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22998808	1		T1	51169		T2	20		T3	58
auto[TlIntgErrNone]	partial	auto[1]	657031	1		T1	771		T2	1		T3	64
auto[TlIntgErrNone]	full_word	auto[0]	3952984	1		T1	2912		T2	1		T4	11962
auto[TlIntgErrNone]	full_word	auto[1]	3771865	1		T1	5388		T3	57		T13	3
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T72	2		T74	2		T215	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T72	5		T74	2		T215	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T215	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T285	1		T258	1		T259	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T72	2		T74	3		T215	4
auto[TlIntgErrData]	partial	auto[1]	31	1		T72	1		T74	2		T215	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T72	1		T215	1		T285	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T363	1		T362	1		T364	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T72	6		T74	1		T215	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T72	3		T215	3		T260	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1		T215	1		T363	1		T259	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T263	1		T359	1		T262	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18031	1		T169	740		T72	17		T74	8
full_word	4118528	1		T5	88		T9	17154		T19	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4136295	1		T5	88		T9	17154		T19	2
auto[TlIntgErrCmd]	94	1		T72	4		T74	7		T215	4
auto[TlIntgErrData]	96	1		T72	8		T74	2		T215	6
auto[TlIntgErrBoth]	74	1		T72	7		T215	7		T260	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4112887	1		T5	88		T9	17154		T19	2
auto[1]	23672	1		T169	1027		T72	12		T74	3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1154	1		T169	36		T170	7		T214	1
auto[TlIntgErrNone]	partial	auto[1]	16639	1		T169	704		T170	57		T214	98
auto[TlIntgErrNone]	full_word	auto[0]	4111614	1		T5	88		T9	17154		T19	2
auto[TlIntgErrNone]	full_word	auto[1]	6888	1		T169	323		T170	12		T214	25
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T72	1		T74	3		T215	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T72	3		T74	3		T215	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T74	1		T258	3		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T258	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1		T72	2		T74	2		T215	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T72	6		T215	2		T260	1
auto[TlIntgErrData]	full_word	auto[0]	8	1		T215	2		T363	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T285	1		T258	1		T259	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T72	4		T215	4		T260	1
auto[TlIntgErrBoth]	partial	auto[1]	34	1		T72	1		T215	3		T263	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T260	1		T285	1		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T72	2		T263	1		T259	1