Unified Coverage Report :: Module :: prim_generic_flash_bank

Module : prim_generic_flash_bank

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank	93.55	96.48	92.86		93.75	91.11
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank	93.55	96.48	92.86		93.75	91.11

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	96.04	90.48		93.75	93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[1].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[2].u_info_mem	95.24	85.71				100.00	100.00
u_cmd_fifo	97.22	100.00	88.89			100.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_phy_cov_if	89.51	100.00	85.19			83.33

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	96.04	90.48		93.75	93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[1].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[2].u_info_mem	95.24	85.71				100.00	100.00
u_cmd_fifo	97.22	100.00	88.89			100.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_phy_cov_if	89.51	100.00	85.19			83.33

Line Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	1	1
152	1	1
153	1	1
175	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	2	2
190	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
210	1	1
211	1	1
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
231	1	1
236	1	1
237	1	1
238	1	1
240	2	2
241	1	2
242	2	2
			MISSING_ELSE
244	2	2
245	2	2
			MISSING_ELSE
251	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
267	1	1
268	1	1
269	1	1
271	1	1
273	1	1
274	1	1
275	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
286	1	1
287	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
			MISSING_ELSE
313	1	1
314	1	1
316	1	1
317	1	1
320	1	1
321	0	1
322	0	1
323	0	1
324	0	1
326	1	1
327	1	1
330	1	1
332	1	1
333	1	1
334	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
346	1	1
347	1	1
348	1	1
349	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
390	1	1
391	1	1
			MISSING_ELSE
402	1	1
426	3	3
446	1	1
447	1	1
450	1	1
453	1	1

---

Cond Coverage for Module : prim_generic_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T59,T60
1	1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T6,T26
0	0	1	0	Covered	T1,T13,T4
0	1	0	0	Covered	T1,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T4
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T4

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T26

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T4
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T45,T59,T60
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T28
0	1	Not Covered
1	0	Covered	T1,T4,T28

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T59,T60

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T77,T78
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T13,T4
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T9,T19,T31
1	1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T31
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T79,T77
1	0	1	Covered	T4,T9,T47
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T9,T6,T80

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T26
1	0	Covered	T9,T47,T80

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T47,T80

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T6,T47
1	0	1	Covered	T4,T9,T19
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T19,T31,T28

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T26
1	0	Covered	T9,T19,T31

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T19,T31

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_generic_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T45,T59,T60
StErase	302	Covered	T1,T13,T4
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T1,T4,T5
StRead	296	Covered	T1,T2,T3
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T61,T63,T81
StErSuspend->StReset	391	Covered	T45,T59,T60
StErase->StErSuspend	356	Covered	T45,T59,T60
StErase->StIdle	364	Covered	T1,T4,T28
StErase->StReset	391	Covered	T13,T52,T45
StIdle->StErase	302	Covered	T1,T13,T4
StIdle->StRead	296	Covered	T1,T2,T3
StIdle->StReset	391	Covered	T1,T13,T4
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T1,T4,T5
StProg->StReset	391	Covered	T45,T59,T60
StRead->StIdle	327	Covered	T1,T2,T3
StRead->StProg	334	Covered	T1,T4,T5
StRead->StReset	391	Covered	T30,T82,T83
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T40,T75,T76

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T13,T4
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T26
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T1,T4,T5
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T4,T5
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T5
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T45,T59,T60
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T13,T4
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T28
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T59,T60
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	1	1
152	1	1
153	1	1
175	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	2	2
190	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
210	1	1
211	1	1
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
231	1	1
236	1	1
237	1	1
238	1	1
240	2	2
241	1	2
242	2	2
			MISSING_ELSE
244	2	2
245	2	2
			MISSING_ELSE
251	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
267	1	1
268	1	1
269	1	1
271	1	1
273	1	1
274	1	1
275	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
286	1	1
287	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
			MISSING_ELSE
313	1	1
314	1	1
316	1	1
317	1	1
320	1	1
321	0	1
322	0	1
323	0	1
324	0	1
326	1	1
327	1	1
330	1	1
332	1	1
333	1	1
334	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
346	1	1
347	1	1
348	1	1
349	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
390	1	1
391	1	1
			MISSING_ELSE
402	1	1
426	3	3
446	1	1
447	1	1
450	1	1
453	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T84
1	1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T6,T26
0	0	1	0	Covered	T1,T13,T4
0	1	0	0	Covered	T1,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T4
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T4

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T26

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T4
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T45,T59,T60
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T28
0	1	Not Covered
1	0	Covered	T1,T4,T28

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T59,T60

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T78,T85
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T13,T4
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T9,T19,T31
1	1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T31
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T78,T85
1	0	1	Covered	T4,T9,T47
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T9,T6,T80

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T26
1	0	Covered	T9,T47,T80

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T47,T80

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T6,T47
1	0	1	Covered	T4,T9,T31
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T19,T31,T28

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T26
1	0	Covered	T9,T19,T31

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T19,T31

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T61,T62,T63
StErase	302	Covered	T1,T13,T4
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T1,T4,T5
StRead	296	Covered	T1,T2,T3
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T61,T63,T81
StErSuspend->StReset	391	Covered	T62,T84
StErase->StErSuspend	356	Covered	T61,T62,T63
StErase->StIdle	364	Covered	T1,T4,T28
StErase->StReset	391	Covered	T13,T52,T45
StIdle->StErase	302	Covered	T1,T13,T4
StIdle->StRead	296	Covered	T1,T2,T3
StIdle->StReset	391	Covered	T1,T13,T4
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T1,T4,T5
StProg->StReset	391	Covered	T45,T59,T60
StRead->StIdle	327	Covered	T1,T2,T3
StRead->StProg	334	Covered	T1,T4,T5
StRead->StReset	391	Covered	T82,T83,T65
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T40,T75,T76

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T13,T4
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T26
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T1,T4,T5
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T4,T5
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T5
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T61,T62,T63
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T13,T4
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T28
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T61,T62,T63
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	1	1
152	1	1
153	1	1
175	1	1
176	1	1
177	1	1
178	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	2	2
190	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
210	1	1
211	1	1
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
231	1	1
236	1	1
237	1	1
238	1	1
240	2	2
241	1	2
242	2	2
			MISSING_ELSE
244	2	2
245	2	2
			MISSING_ELSE
251	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
267	1	1
268	1	1
269	1	1
271	1	1
273	1	1
274	1	1
275	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
286	1	1
287	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
			MISSING_ELSE
313	1	1
314	1	1
316	1	1
317	1	1
320	1	1
321	0	1
322	0	1
323	0	1
324	0	1
326	1	1
327	1	1
330	1	1
332	1	1
333	1	1
334	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
346	1	1
347	1	1
348	1	1
349	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
390	1	1
391	1	1
			MISSING_ELSE
402	1	1
426	3	3
446	1	1
447	1	1
450	1	1
453	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T59,T60
1	1	Covered	T4,T5,T9

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T6,T27
0	0	1	0	Covered	T4,T28,T29
0	1	0	0	Covered	T4,T5,T30
1	0	0	0	Covered	T4,T5,T9

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T30
1	1	Covered	T4,T5,T9

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T30

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T28,T29

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T6,T27

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T4,T5,T9

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T40,T75,T76
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T45,T59,T60
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T29
0	1	Not Covered
1	0	Covered	T4,T28,T29

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T59,T60

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T29,T6
1	1	Covered	T4,T5,T9

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T6
0	1	Covered	T6,T77,T86
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T6,T32
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T29,T80,T87
1	1	1	Covered	T28,T29,T6

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T29,T6

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T31
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T79,T77
1	0	1	Covered	T4,T9,T47
1	1	0	Covered	T28,T29,T6
1	1	1	Covered	T6,T80,T79

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T29,T6

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T27
1	0	Covered	T9,T47,T80

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T47,T80

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T80,T88
1	0	1	Covered	T4,T9,T19
1	1	0	Covered	T28,T29,T6
1	1	1	Covered	T29,T6,T80

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T29,T6

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T27
1	0	Covered	T9,T19,T31

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T19,T31

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T28,T29,T6
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T45,T59,T60
StErase	302	Covered	T4,T28,T29
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T4,T5,T30
StRead	296	Covered	T4,T5,T9
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T61,T63,T81
StErSuspend->StReset	391	Covered	T45,T59,T60
StErase->StErSuspend	356	Covered	T45,T59,T60
StErase->StIdle	364	Covered	T4,T28,T29
StErase->StReset	391	Covered	T45,T59,T60
StIdle->StErase	302	Covered	T4,T28,T29
StIdle->StRead	296	Covered	T4,T5,T9
StIdle->StReset	391	Covered	T1,T13,T4
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T4,T5,T30
StProg->StReset	391	Covered	T45,T59,T60
StRead->StIdle	327	Covered	T4,T5,T9
StRead->StProg	334	Covered	T4,T5,T30
StRead->StReset	391	Covered	T30,T89
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T40,T75,T76

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T29,T6

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T4,T5,T9
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T4,T5,T9
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T30
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T28,T29
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T27
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T30
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T4,T5,T9
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T4,T5,T30
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T30
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T5,T30
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T45,T59,T60
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T28,T29
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T28,T29
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T59,T60
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3