Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1557049792	1553812668	0	0
CheckNGreaterZero_A	4088	4088	0	0
GntImpliesReady_A	1557049792	404693616	0	0
GntImpliesValid_A	1557049792	404693616	0	0
GrantKnown_A	1557049792	1553812668	0	0
IdxKnown_A	1557049792	1553812668	0	0
IndexIsCorrect_A	1557049792	404693616	0	0
NoReadyValidNoGrant_A	1557049792	174297218	0	0
Priority_A	1557049792	429079128	0	0
ReadyAndValidImplyGrant_A	1557049792	404693616	0	0
ReqAndReadyImplyGrant_A	1557049792	404693616	0	0
ReqImpliesValid_A	1557049792	429079128	0	0
ValidKnown_A	1557049792	1553812668	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	1553812668	0	0
T1	540716	509000	0	0
T2	4800	4588	0	0
T3	15764	15452	0	0
T4	3217924	3217832	0	0
T5	371012	370736	0	0
T9	247036	246712	0	0
T13	14292	11728	0	0
T14	4704	3632	0	0
T18	5236	4252	0	0
T19	11820	11324	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4088	4088	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	404693616	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153264	0	0
T6	0	1319130	0	0
T9	247036	48548	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	404693616	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153264	0	0
T6	0	1319130	0	0
T9	247036	48548	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	1553812668	0	0
T1	540716	509000	0	0
T2	4800	4588	0	0
T3	15764	15452	0	0
T4	3217924	3217832	0	0
T5	371012	370736	0	0
T9	247036	246712	0	0
T13	14292	11728	0	0
T14	4704	3632	0	0
T18	5236	4252	0	0
T19	11820	11324	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	1553812668	0	0
T1	540716	509000	0	0
T2	4800	4588	0	0
T3	15764	15452	0	0
T4	3217924	3217832	0	0
T5	371012	370736	0	0
T9	247036	246712	0	0
T13	14292	11728	0	0
T14	4704	3632	0	0
T18	5236	4252	0	0
T19	11820	11324	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	404693616	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153264	0	0
T6	0	1319130	0	0
T9	247036	48548	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	174297218	0	0
T1	270358	39712	0	0
T2	2400	256	0	0
T3	7882	256	0	0
T4	3217924	425034	0	0
T5	371012	4096	0	0
T6	0	1734	0	0
T7	0	250	0	0
T9	247036	62668	0	0
T13	7146	1102	0	0
T14	4704	536	0	0
T18	5236	536	0	0
T19	11820	716	0	0
T28	0	3372	0	0
T29	0	230	0	0
T30	3742	0	0	0
T31	3470	48	0	0
T45	0	64	0	0
T57	8614	0	0	0
T58	14830	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	429079128	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153280	0	0
T6	0	1319130	0	0
T9	247036	77908	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	404693616	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153264	0	0
T6	0	1319130	0	0
T9	247036	48548	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	404693616	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153264	0	0
T6	0	1319130	0	0
T9	247036	48548	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	429079128	0	0
T1	270358	169056	0	0
T2	2400	64	0	0
T3	7882	64	0	0
T4	3217924	1089042	0	0
T5	371012	153280	0	0
T6	0	1319130	0	0
T9	247036	77908	0	0
T13	7146	300	0	0
T14	4704	134	0	0
T18	5236	134	0	0
T19	11820	902	0	0
T28	0	57506	0	0
T29	0	1132	0	0
T30	3742	552	0	0
T31	3470	18	0	0
T45	0	18934	0	0
T57	8614	0	0	0
T58	14830	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557049792	1553812668	0	0
T1	540716	509000	0	0
T2	4800	4588	0	0
T3	15764	15452	0	0
T4	3217924	3217832	0	0
T5	371012	370736	0	0
T9	247036	246712	0	0
T13	14292	11728	0	0
T14	4704	3632	0	0
T18	5236	4252	0	0
T19	11820	11324	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389262448	388453167	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	389262448	100002064	0	0
GntImpliesValid_A	389262448	100002064	0	0
GrantKnown_A	389262448	388453167	0	0
IdxKnown_A	389262448	388453167	0	0
IndexIsCorrect_A	389262448	100002064	0	0
NoReadyValidNoGrant_A	389262448	44349546	0	0
Priority_A	389262448	106051920	0	0
ReadyAndValidImplyGrant_A	389262448	100002064	0	0
ReqAndReadyImplyGrant_A	389262448	100002064	0	0
ReqImpliesValid_A	389262448	106051920	0	0
ValidKnown_A	389262448	388453167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	44349546	0	0
T1	135179	19856	0	0
T2	1200	128	0	0
T3	3941	128	0	0
T4	804481	107353	0	0
T5	92753	625	0	0
T9	61759	17392	0	0
T13	3573	551	0	0
T14	1176	268	0	0
T18	1309	268	0	0
T19	2955	335	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	106051920	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25834	0	0
T9	61759	22041	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	106051920	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25834	0	0
T9	61759	22041	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389262448	388453167	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	389262448	100002064	0	0
GntImpliesValid_A	389262448	100002064	0	0
GrantKnown_A	389262448	388453167	0	0
IdxKnown_A	389262448	388453167	0	0
IndexIsCorrect_A	389262448	100002064	0	0
NoReadyValidNoGrant_A	389262448	44349546	0	0
Priority_A	389262448	106051920	0	0
ReadyAndValidImplyGrant_A	389262448	100002064	0	0
ReqAndReadyImplyGrant_A	389262448	100002064	0	0
ReqImpliesValid_A	389262448	106051920	0	0
ValidKnown_A	389262448	388453167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	44349546	0	0
T1	135179	19856	0	0
T2	1200	128	0	0
T3	3941	128	0	0
T4	804481	107353	0	0
T5	92753	625	0	0
T9	61759	17392	0	0
T13	3573	551	0	0
T14	1176	268	0	0
T18	1309	268	0	0
T19	2955	335	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	106051920	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25834	0	0
T9	61759	22041	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	100002064	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25829	0	0
T9	61759	13751	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	106051920	0	0
T1	135179	84528	0	0
T2	1200	32	0	0
T3	3941	32	0	0
T4	804481	274908	0	0
T5	92753	25834	0	0
T9	61759	22041	0	0
T13	3573	150	0	0
T14	1176	67	0	0
T18	1309	67	0	0
T19	2955	443	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
1	0	Covered	T5,T9,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T19
1	0	Covered	T4,T5,T9
1	1	Covered	T5,T9,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T4,T5,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T4,T5,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389262448	388453167	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	389262448	102344744	0	0
GntImpliesValid_A	389262448	102344744	0	0
GrantKnown_A	389262448	388453167	0	0
IdxKnown_A	389262448	388453167	0	0
IndexIsCorrect_A	389262448	102344744	0	0
NoReadyValidNoGrant_A	389262448	42799063	0	0
Priority_A	389262448	108487644	0	0
ReadyAndValidImplyGrant_A	389262448	102344744	0	0
ReqAndReadyImplyGrant_A	389262448	102344744	0	0
ReqImpliesValid_A	389262448	108487644	0	0
ValidKnown_A	389262448	388453167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	42799063	0	0
T4	804481	105164	0	0
T5	92753	1423	0	0
T6	0	867	0	0
T7	0	125	0	0
T9	61759	13942	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	23	0	0
T28	0	1686	0	0
T29	0	115	0	0
T30	1871	0	0	0
T31	1735	24	0	0
T45	0	32	0	0
T57	4307	0	0	0
T58	7415	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	108487644	0	0
T4	804481	269613	0	0
T5	92753	50806	0	0
T6	0	659565	0	0
T9	61759	16913	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	108487644	0	0
T4	804481	269613	0	0
T5	92753	50806	0	0
T6	0	659565	0	0
T9	61759	16913	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
1	0	Covered	T5,T9,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T9,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T19
1	0	Covered	T4,T5,T9
1	1	Covered	T5,T9,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T4,T5,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T19
1	1	Covered	T4,T5,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T9,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389262448	388453167	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	389262448	102344744	0	0
GntImpliesValid_A	389262448	102344744	0	0
GrantKnown_A	389262448	388453167	0	0
IdxKnown_A	389262448	388453167	0	0
IndexIsCorrect_A	389262448	102344744	0	0
NoReadyValidNoGrant_A	389262448	42799063	0	0
Priority_A	389262448	108487644	0	0
ReadyAndValidImplyGrant_A	389262448	102344744	0	0
ReqAndReadyImplyGrant_A	389262448	102344744	0	0
ReqImpliesValid_A	389262448	108487644	0	0
ValidKnown_A	389262448	388453167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	42799063	0	0
T4	804481	105164	0	0
T5	92753	1423	0	0
T6	0	867	0	0
T7	0	125	0	0
T9	61759	13942	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	23	0	0
T28	0	1686	0	0
T29	0	115	0	0
T30	1871	0	0	0
T31	1735	24	0	0
T45	0	32	0	0
T57	4307	0	0	0
T58	7415	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	108487644	0	0
T4	804481	269613	0	0
T5	92753	50806	0	0
T6	0	659565	0	0
T9	61759	16913	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	102344744	0	0
T4	804481	269613	0	0
T5	92753	50803	0	0
T6	0	659565	0	0
T9	61759	10523	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	108487644	0	0
T4	804481	269613	0	0
T5	92753	50806	0	0
T6	0	659565	0	0
T9	61759	16913	0	0
T14	1176	0	0	0
T18	1309	0	0	0
T19	2955	8	0	0
T28	0	28753	0	0
T29	0	566	0	0
T30	1871	276	0	0
T31	1735	9	0	0
T45	0	9467	0	0
T57	4307	0	0	0
T58	7415	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389262448	388453167	0	0
T1	135179	127250	0	0
T2	1200	1147	0	0
T3	3941	3863	0	0
T4	804481	804458	0	0
T5	92753	92684	0	0
T9	61759	61678	0	0
T13	3573	2932	0	0
T14	1176	908	0	0
T18	1309	1063	0	0
T19	2955	2831	0	0