Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 88.89 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 88.89 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 97.75 90.57 100.00 93.48 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 88.89 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 88.89 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.38 96.63 83.96 100.00 91.30 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 1 1
42 1 1
47 1 1
48 1 1
49 1 1
50 1 1
52 1 1
54 1 1
56 1 1
57 1 1
MISSING_ELSE
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
73 1 1
74 1 1
75 1 1
==> MISSING_ELSE
83 1 1
84 1 1
85 1 1


Cond Coverage for Module : flash_phy_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T13,T4

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T26
10CoveredT1,T13,T4

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT1,T13,T4
10Not Covered
11CoveredT45,T59,T60

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T13,T4
11CoveredT1,T13,T4

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT4,T6,T26

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T13,T4
10CoveredT45,T59,T60
11CoveredT45,T59,T60

FSM Coverage for Module : flash_phy_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T1,T13,T4
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T45,T59,T60


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T1,T13,T4
StEraseBusy->StEraseSuspend 65 Covered T45,T59,T60
StEraseIdle->StEraseBusy 57 Covered T1,T13,T4
StEraseSuspend->StEraseIdle 75 Covered T45,T59,T60



Branch Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
Branches 10 8 80.00
IF 39 2 2 100.00
CASE 52 8 6 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 52 case (state_q) -2-: 56 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 64 if ((suspend_req_i && ack_i)) -4-: 66 if (done_i) -5-: 73 if (done_i)

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T1,T13,T4
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T45,T59,T60
StEraseBusy - 0 1 - Covered T1,T4,T28
StEraseBusy - 0 0 - Covered T1,T13,T4
StEraseSuspend - - - 1 Covered T45,T59,T60
StEraseSuspend - - - 0 Not Covered
default - - - - Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 1 1
42 1 1
47 1 1
48 1 1
49 1 1
50 1 1
52 1 1
54 1 1
56 1 1
57 1 1
MISSING_ELSE
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
73 1 1
74 1 1
75 1 1
==> MISSING_ELSE
83 1 1
84 1 1
85 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T13,T4

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T26
10CoveredT1,T13,T4

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT1,T13,T4
10Not Covered
11CoveredT61,T62,T63

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T13,T4
11CoveredT1,T13,T4

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT4,T6,T26

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T13,T4
10CoveredT45,T59,T60
11CoveredT61,T62,T63

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T1,T13,T4
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T61,T62,T63


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T1,T13,T4
StEraseBusy->StEraseSuspend 65 Covered T61,T62,T63
StEraseIdle->StEraseBusy 57 Covered T1,T13,T4
StEraseSuspend->StEraseIdle 75 Covered T61,T62,T63



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
Branches 10 8 80.00
IF 39 2 2 100.00
CASE 52 8 6 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 52 case (state_q) -2-: 56 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 64 if ((suspend_req_i && ack_i)) -4-: 66 if (done_i) -5-: 73 if (done_i)

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T1,T13,T4
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T61,T62,T63
StEraseBusy - 0 1 - Covered T1,T4,T28
StEraseBusy - 0 0 - Covered T1,T13,T4
StEraseSuspend - - - 1 Covered T61,T62,T63
StEraseSuspend - - - 0 Not Covered
default - - - - Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 1 1
42 1 1
47 1 1
48 1 1
49 1 1
50 1 1
52 1 1
54 1 1
56 1 1
57 1 1
MISSING_ELSE
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
73 1 1
74 1 1
75 1 1
==> MISSING_ELSE
83 1 1
84 1 1
85 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T28,T29

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T27
10CoveredT4,T28,T29

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT4,T28,T29
10Not Covered
11CoveredT45,T59,T60

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T28,T29
11CoveredT4,T28,T29

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T27
11CoveredT4,T6,T27

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT4,T28,T29
10CoveredT45,T59,T60
11CoveredT45,T59,T60

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T4,T28,T29
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T45,T59,T60


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T4,T28,T29
StEraseBusy->StEraseSuspend 65 Covered T45,T59,T60
StEraseIdle->StEraseBusy 57 Covered T4,T28,T29
StEraseSuspend->StEraseIdle 75 Covered T45,T59,T60



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
Branches 10 8 80.00
IF 39 2 2 100.00
CASE 52 8 6 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 52 case (state_q) -2-: 56 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 64 if ((suspend_req_i && ack_i)) -4-: 66 if (done_i) -5-: 73 if (done_i)

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T4,T28,T29
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T45,T59,T60
StEraseBusy - 0 1 - Covered T4,T28,T29
StEraseBusy - 0 0 - Covered T4,T28,T29
StEraseSuspend - - - 1 Covered T45,T59,T60
StEraseSuspend - - - 0 Not Covered
default - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%