Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24842817	1		T1	61		T2	120		T3	117
full_word	7522872	1		T1	46		T2	41		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32365409	1		T1	107		T2	161		T3	119
auto[TlIntgErrCmd]	84	1		T207	3		T208	6		T219	2
auto[TlIntgErrData]	101	1		T207	5		T208	6		T219	6
auto[TlIntgErrBoth]	95	1		T207	2		T208	8		T219	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27915667	1		T1	60		T2	115		T3	110
auto[1]	4450022	1		T1	47		T2	46		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24147068	1		T1	59		T2	113		T3	109
auto[TlIntgErrNone]	partial	auto[1]	695485	1		T1	2		T2	7		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	3768476	1		T1	1		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3754380	1		T1	45		T2	39		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T207	1		T208	2		T232	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T207	2		T208	3		T219	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T208	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T232	1		T261	1		T275	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T207	3		T208	2		T219	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T207	2		T208	2		T219	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T230	1		T269	1		T280	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T208	2		T368	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T208	2		T232	5		T261	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T207	2		T208	6		T219	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T219	1		T366	1		T280	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T230	1		T274	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18300	1		T207	7		T208	17		T209	132
full_word	3892036	1		T5	16862		T6	42043		T9	16858

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3910073	1		T5	16862		T6	42043		T9	16858
auto[TlIntgErrCmd]	88	1		T207	3		T208	6		T219	6
auto[TlIntgErrData]	93	1		T207	4		T208	6		T219	1
auto[TlIntgErrBoth]	82	1		T207	2		T208	7		T219	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3886982	1		T5	16862		T6	42043		T9	16858
auto[1]	23354	1		T207	5		T208	9		T209	160

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1327	1		T209	8		T217	23		T218	10
auto[TlIntgErrNone]	partial	auto[1]	16737	1		T209	124		T217	316		T218	121
auto[TlIntgErrNone]	full_word	auto[0]	3885538	1		T5	16862		T6	42043		T9	16858
auto[TlIntgErrNone]	full_word	auto[1]	6471	1		T209	36		T217	87		T218	37
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T207	1		T208	4		T219	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T207	1		T208	1		T219	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T207	1		T208	1		T232	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T368	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1		T207	2		T208	2		T232	1
auto[TlIntgErrData]	partial	auto[1]	43	1		T207	1		T208	4		T219	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T261	1		T230	1		T372	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T207	1		T232	1		T366	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T208	2		T219	1		T232	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T207	2		T208	4		T219	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T208	1		T274	1		T368	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T369	1		T368	1		-	-