Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1487713560	1484152812	0	0
CheckNGreaterZero_A	4056	4056	0	0
GntImpliesReady_A	1487713560	394214289	0	0
GntImpliesValid_A	1487713560	394214289	0	0
GrantKnown_A	1487713560	1484152812	0	0
IdxKnown_A	1487713560	1484152812	0	0
IndexIsCorrect_A	1487713560	394214289	0	0
NoReadyValidNoGrant_A	1487713560	176188445	0	0
Priority_A	1487713560	417500562	0	0
ReadyAndValidImplyGrant_A	1487713560	394214289	0	0
ReqAndReadyImplyGrant_A	1487713560	394214289	0	0
ReqImpliesValid_A	1487713560	417500562	0	0
ValidKnown_A	1487713560	1484152812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	1484152812	0	0
T1	4440	3500	0	0
T2	1926728	1926208	0	0
T3	12980	10280	0	0
T4	228064	227860	0	0
T5	216208	215920	0	0
T6	1430108	1429816	0	0
T9	434724	434332	0	0
T13	13420	10412	0	0
T17	6896	6616	0	0
T18	128524	128128	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4056	4056	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	394214289	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	45450	0	0
T6	1430108	495292	0	0
T7	5576	890	0	0
T9	434724	134530	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	47946	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	394214289	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	45450	0	0
T6	1430108	495292	0	0
T7	5576	890	0	0
T9	434724	134530	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	47946	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	1484152812	0	0
T1	4440	3500	0	0
T2	1926728	1926208	0	0
T3	12980	10280	0	0
T4	228064	227860	0	0
T5	216208	215920	0	0
T6	1430108	1429816	0	0
T9	434724	434332	0	0
T13	13420	10412	0	0
T17	6896	6616	0	0
T18	128524	128128	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	1484152812	0	0
T1	4440	3500	0	0
T2	1926728	1926208	0	0
T3	12980	10280	0	0
T4	228064	227860	0	0
T5	216208	215920	0	0
T6	1430108	1429816	0	0
T9	434724	434332	0	0
T13	13420	10412	0	0
T17	6896	6616	0	0
T18	128524	128128	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	394214289	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	45450	0	0
T6	1430108	495292	0	0
T7	5576	890	0	0
T9	434724	134530	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	47946	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	176188445	0	0
T1	2220	520	0	0
T2	963364	256	0	0
T3	6490	832	0	0
T4	114032	6784	0	0
T5	216208	57544	0	0
T6	1430108	173286	0	0
T7	5576	0	0	0
T9	434724	77634	0	0
T13	13420	1152	0	0
T17	6896	256	0	0
T18	128524	2688	0	0
T20	0	806400	0	0
T24	0	126	0	0
T25	0	100	0	0
T39	197226	57412	0	0
T53	0	92	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T66	0	88	0	0
T67	0	3446	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	417500562	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	74662	0	0
T6	1430108	572402	0	0
T7	5576	890	0	0
T9	434724	162642	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	53076	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	394214289	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	45450	0	0
T6	1430108	495292	0	0
T7	5576	890	0	0
T9	434724	134530	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	47946	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	394214289	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	45450	0	0
T6	1430108	495292	0	0
T7	5576	890	0	0
T9	434724	134530	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	47946	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	417500562	0	0
T1	2220	130	0	0
T2	963364	1078	0	0
T3	6490	234	0	0
T4	114032	31752	0	0
T5	216208	74662	0	0
T6	1430108	572402	0	0
T7	5576	890	0	0
T9	434724	162642	0	0
T13	13420	288	0	0
T17	6896	64	0	0
T18	128524	1608	0	0
T19	0	4366	0	0
T24	0	630	0	0
T39	197226	53076	0	0
T53	0	16908	0	0
T55	3002	0	0	0
T56	3664	0	0	0
T61	0	172224	0	0
T64	0	181284	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487713560	1484152812	0	0
T1	4440	3500	0	0
T2	1926728	1926208	0	0
T3	12980	10280	0	0
T4	228064	227860	0	0
T5	216208	215920	0	0
T6	1430108	1429816	0	0
T9	434724	434332	0	0
T13	13420	10412	0	0
T17	6896	6616	0	0
T18	128524	128128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371928390	371038203	0	0
CheckNGreaterZero_A	1014	1014	0	0
GntImpliesReady_A	371928390	93679820	0	0
GntImpliesValid_A	371928390	93679820	0	0
GrantKnown_A	371928390	371038203	0	0
IdxKnown_A	371928390	371038203	0	0
IndexIsCorrect_A	371928390	93679820	0	0
NoReadyValidNoGrant_A	371928390	44687356	0	0
Priority_A	371928390	99459502	0	0
ReadyAndValidImplyGrant_A	371928390	93679820	0	0
ReqAndReadyImplyGrant_A	371928390	93679820	0	0
ReqImpliesValid_A	371928390	99459502	0	0
ValidKnown_A	371928390	371038203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679820	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679820	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679820	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	44687356	0	0
T1	1110	260	0	0
T2	481682	128	0	0
T3	3245	416	0	0
T4	57016	3392	0	0
T5	54052	15583	0	0
T6	357527	46513	0	0
T9	108681	19288	0	0
T13	3355	576	0	0
T17	1724	128	0	0
T18	32131	1344	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	99459502	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	19387	0	0
T6	357527	132190	0	0
T9	108681	42224	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679820	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679820	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	99459502	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	19387	0	0
T6	357527	132190	0	0
T9	108681	42224	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371928390	371038203	0	0
CheckNGreaterZero_A	1014	1014	0	0
GntImpliesReady_A	371928390	93679659	0	0
GntImpliesValid_A	371928390	93679659	0	0
GrantKnown_A	371928390	371038203	0	0
IdxKnown_A	371928390	371038203	0	0
IndexIsCorrect_A	371928390	93679659	0	0
NoReadyValidNoGrant_A	371928390	44687285	0	0
Priority_A	371928390	99459412	0	0
ReadyAndValidImplyGrant_A	371928390	93679659	0	0
ReqAndReadyImplyGrant_A	371928390	93679659	0	0
ReqImpliesValid_A	371928390	99459412	0	0
ValidKnown_A	371928390	371038203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679659	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679659	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679659	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	44687285	0	0
T1	1110	260	0	0
T2	481682	128	0	0
T3	3245	416	0	0
T4	57016	3392	0	0
T5	54052	15583	0	0
T6	357527	46513	0	0
T9	108681	19288	0	0
T13	3355	576	0	0
T17	1724	128	0	0
T18	32131	1344	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	99459412	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	19387	0	0
T6	357527	132190	0	0
T9	108681	42224	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679659	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	93679659	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	12023	0	0
T6	357527	110285	0	0
T9	108681	36171	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	99459412	0	0
T1	1110	65	0	0
T2	481682	539	0	0
T3	3245	117	0	0
T4	57016	15876	0	0
T5	54052	19387	0	0
T6	357527	132190	0	0
T9	108681	42224	0	0
T13	3355	144	0	0
T17	1724	32	0	0
T18	32131	804	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371928390	371038203	0	0
CheckNGreaterZero_A	1014	1014	0	0
GntImpliesReady_A	371928390	103427405	0	0
GntImpliesValid_A	371928390	103427405	0	0
GrantKnown_A	371928390	371038203	0	0
IdxKnown_A	371928390	371038203	0	0
IndexIsCorrect_A	371928390	103427405	0	0
NoReadyValidNoGrant_A	371928390	43406902	0	0
Priority_A	371928390	109290824	0	0
ReadyAndValidImplyGrant_A	371928390	103427405	0	0
ReqAndReadyImplyGrant_A	371928390	103427405	0	0
ReqImpliesValid_A	371928390	109290824	0	0
ValidKnown_A	371928390	371038203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	43406902	0	0
T5	54052	13189	0	0
T6	357527	40130	0	0
T7	2788	0	0	0
T9	108681	19529	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T20	0	403200	0	0
T24	0	63	0	0
T25	0	50	0	0
T39	98613	28706	0	0
T53	0	46	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T66	0	44	0	0
T67	0	1723	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	109290824	0	0
T5	54052	17944	0	0
T6	357527	154011	0	0
T7	2788	445	0	0
T9	108681	39097	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	26538	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	109290824	0	0
T5	54052	17944	0	0
T6	357527	154011	0	0
T7	2788	445	0	0
T9	108681	39097	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	26538	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371928390	371038203	0	0
CheckNGreaterZero_A	1014	1014	0	0
GntImpliesReady_A	371928390	103427405	0	0
GntImpliesValid_A	371928390	103427405	0	0
GrantKnown_A	371928390	371038203	0	0
IdxKnown_A	371928390	371038203	0	0
IndexIsCorrect_A	371928390	103427405	0	0
NoReadyValidNoGrant_A	371928390	43406902	0	0
Priority_A	371928390	109290824	0	0
ReadyAndValidImplyGrant_A	371928390	103427405	0	0
ReqAndReadyImplyGrant_A	371928390	103427405	0	0
ReqImpliesValid_A	371928390	109290824	0	0
ValidKnown_A	371928390	371038203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	43406902	0	0
T5	54052	13189	0	0
T6	357527	40130	0	0
T7	2788	0	0	0
T9	108681	19529	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T20	0	403200	0	0
T24	0	63	0	0
T25	0	50	0	0
T39	98613	28706	0	0
T53	0	46	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T66	0	44	0	0
T67	0	1723	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	109290824	0	0
T5	54052	17944	0	0
T6	357527	154011	0	0
T7	2788	445	0	0
T9	108681	39097	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	26538	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	103427405	0	0
T5	54052	10702	0	0
T6	357527	137361	0	0
T7	2788	445	0	0
T9	108681	31094	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	23973	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	109290824	0	0
T5	54052	17944	0	0
T6	357527	154011	0	0
T7	2788	445	0	0
T9	108681	39097	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T19	0	2183	0	0
T24	0	315	0	0
T39	98613	26538	0	0
T53	0	8454	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T61	0	86112	0	0
T64	0	90642	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0