Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25760443	1		T1	66		T2	111		T3	85
full_word	7764813	1		T1	40		T2	1		T3	65

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33524936	1		T1	106		T2	112		T3	150
auto[TlIntgErrCmd]	112	1		T206	8		T207	10		T227	3
auto[TlIntgErrData]	105	1		T206	4		T207	5		T227	6
auto[TlIntgErrBoth]	103	1		T206	8		T207	5		T227	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28930324	1		T1	59		T2	104		T3	100
auto[1]	4594932	1		T1	47		T2	8		T3	50

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25030809	1		T1	59		T2	104		T3	81
auto[TlIntgErrNone]	partial	auto[1]	729344	1		T1	7		T2	7		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	3899382	1		T3	19		T4	295		T5	9217
auto[TlIntgErrNone]	full_word	auto[1]	3865401	1		T1	40		T2	1		T3	46
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T206	2		T207	4		T227	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T206	4		T207	5		T229	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T207	1		T261	1		T269	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T206	2		T227	1		T262	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T206	2		T207	1		T227	2
auto[TlIntgErrData]	partial	auto[1]	50	1		T206	1		T207	3		T227	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T227	1		T263	1		T268	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T206	1		T207	1		T261	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T206	2		T207	1		T227	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T206	6		T207	3		T229	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T269	1		T357	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T207	1		T257	1		T296	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21619	1		T69	338		T70	82		T71	420
full_word	4064836	1		T4	9		T5	40593		T24	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4086158	1		T4	9		T5	40593		T24	24
auto[TlIntgErrCmd]	96	1		T206	7		T207	6		T227	1
auto[TlIntgErrData]	98	1		T206	8		T207	6		T227	2
auto[TlIntgErrBoth]	103	1		T206	4		T207	7		T227	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4059038	1		T4	9		T5	40593		T24	24
auto[1]	27417	1		T69	372		T70	86		T71	507

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1485	1		T69	20		T70	6		T71	23
auto[TlIntgErrNone]	partial	auto[1]	19857	1		T69	318		T70	76		T71	397
auto[TlIntgErrNone]	full_word	auto[0]	4057429	1		T4	9		T5	40593		T24	24
auto[TlIntgErrNone]	full_word	auto[1]	7387	1		T69	54		T70	10		T71	110
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T206	2		T207	3		T229	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T206	3		T207	3		T227	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T206	1		T358	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T206	1		T229	1		T262	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T206	3		T207	3		T229	3
auto[TlIntgErrData]	partial	auto[1]	49	1		T206	5		T207	3		T227	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T263	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T256	2		T265	1		T263	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T206	1		T207	4		T227	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T206	2		T207	3		T227	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T206	1		T357	1		T359	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T268	1		T358	1		-	-