Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1466162784	1462754656	0	0
CheckNGreaterZero_A	4088	4088	0	0
GntImpliesReady_A	1466162784	402785521	0	0
GntImpliesValid_A	1466162784	402785521	0	0
GrantKnown_A	1466162784	1462754656	0	0
IdxKnown_A	1466162784	1462754656	0	0
IndexIsCorrect_A	1466162784	402785521	0	0
NoReadyValidNoGrant_A	1466162784	177265722	0	0
Priority_A	1466162784	427460557	0	0
ReadyAndValidImplyGrant_A	1466162784	402785521	0	0
ReqAndReadyImplyGrant_A	1466162784	402785521	0	0
ReqImpliesValid_A	1466162784	427460557	0	0
ValidKnown_A	1466162784	1462754656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	1462754656	0	0
T1	4576	3688	0	0
T2	14116	11616	0	0
T3	2676	2380	0	0
T4	17476	17044	0	0
T5	1342216	1341996	0	0
T9	7376	6912	0	0
T13	3850984	3850324	0	0
T17	4232	3936	0	0
T18	818380	818148	0	0
T19	3100	2792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4088	4088	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	402785521	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	462126	0	0
T6	0	2334	0	0
T7	0	115484	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	402785521	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	462126	0	0
T6	0	2334	0	0
T7	0	115484	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	1462754656	0	0
T1	4576	3688	0	0
T2	14116	11616	0	0
T3	2676	2380	0	0
T4	17476	17044	0	0
T5	1342216	1341996	0	0
T9	7376	6912	0	0
T13	3850984	3850324	0	0
T17	4232	3936	0	0
T18	818380	818148	0	0
T19	3100	2792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	1462754656	0	0
T1	4576	3688	0	0
T2	14116	11616	0	0
T3	2676	2380	0	0
T4	17476	17044	0	0
T5	1342216	1341996	0	0
T9	7376	6912	0	0
T13	3850984	3850324	0	0
T17	4232	3936	0	0
T18	818380	818148	0	0
T19	3100	2792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	402785521	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	462126	0	0
T6	0	2334	0	0
T7	0	115484	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	177265722	0	0
T1	2288	536	0	0
T2	7058	1166	0	0
T3	2676	294	0	0
T4	17476	1750	0	0
T5	1342216	192680	0	0
T6	0	72	0	0
T7	0	73952	0	0
T8	0	14	0	0
T9	7376	512	0	0
T13	3850984	384	0	0
T17	4232	256	0	0
T18	818380	988	0	0
T19	3100	256	0	0
T22	0	125424	0	0
T24	1578	0	0	0
T27	0	8	0	0
T48	0	140	0	0
T61	3308	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	427460557	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	521648	0	0
T6	0	2334	0	0
T7	0	137916	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	402785521	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	462126	0	0
T6	0	2334	0	0
T7	0	115484	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	402785521	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	462126	0	0
T6	0	2334	0	0
T7	0	115484	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	427460557	0	0
T1	2288	134	0	0
T2	7058	292	0	0
T3	2676	78	0	0
T4	17476	2230	0	0
T5	1342216	521648	0	0
T6	0	2334	0	0
T7	0	137916	0	0
T9	7376	140	0	0
T13	3850984	1418	0	0
T17	4232	64	0	0
T18	818380	402372	0	0
T19	3100	64	0	0
T20	0	552	0	0
T24	1578	0	0	0
T26	0	1364734	0	0
T27	0	2	0	0
T48	0	659056	0	0
T61	3308	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466162784	1462754656	0	0
T1	4576	3688	0	0
T2	14116	11616	0	0
T3	2676	2380	0	0
T4	17476	17044	0	0
T5	1342216	1341996	0	0
T9	7376	6912	0	0
T13	3850984	3850324	0	0
T17	4232	3936	0	0
T18	818380	818148	0	0
T19	3100	2792	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	366540696	365688664	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	366540696	103762152	0	0
GntImpliesValid_A	366540696	103762152	0	0
GrantKnown_A	366540696	365688664	0	0
IdxKnown_A	366540696	365688664	0	0
IndexIsCorrect_A	366540696	103762152	0	0
NoReadyValidNoGrant_A	366540696	45939660	0	0
Priority_A	366540696	109869759	0	0
ReadyAndValidImplyGrant_A	366540696	103762152	0	0
ReqAndReadyImplyGrant_A	366540696	103762152	0	0
ReqImpliesValid_A	366540696	109869759	0	0
ValidKnown_A	366540696	365688664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762152	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762152	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762152	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	45939660	0	0
T1	1144	268	0	0
T2	3529	583	0	0
T3	669	128	0	0
T4	4369	644	0	0
T5	335554	52953	0	0
T9	1844	256	0	0
T13	962746	192	0	0
T17	1058	128	0	0
T18	204595	337	0	0
T19	775	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	109869759	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	152942	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762152	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762152	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	109869759	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	152942	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T24
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T24

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T24
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T24

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	366540696	365688664	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	366540696	103762195	0	0
GntImpliesValid_A	366540696	103762195	0	0
GrantKnown_A	366540696	365688664	0	0
IdxKnown_A	366540696	365688664	0	0
IndexIsCorrect_A	366540696	103762195	0	0
NoReadyValidNoGrant_A	366540696	45939606	0	0
Priority_A	366540696	109869856	0	0
ReadyAndValidImplyGrant_A	366540696	103762195	0	0
ReqAndReadyImplyGrant_A	366540696	103762195	0	0
ReqImpliesValid_A	366540696	109869856	0	0
ValidKnown_A	366540696	365688664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762195	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762195	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762195	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	45939606	0	0
T1	1144	268	0	0
T2	3529	583	0	0
T3	669	128	0	0
T4	4369	644	0	0
T5	335554	52953	0	0
T9	1844	256	0	0
T13	962746	192	0	0
T17	1058	128	0	0
T18	204595	337	0	0
T19	775	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	109869856	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	152942	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762195	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103762195	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	136204	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	109869856	0	0
T1	1144	67	0	0
T2	3529	146	0	0
T3	669	32	0	0
T4	4369	1013	0	0
T5	335554	152942	0	0
T9	1844	70	0	0
T13	962746	709	0	0
T17	1058	32	0	0
T18	204595	66766	0	0
T19	775	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	366540696	365688664	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	366540696	97630526	0	0
GntImpliesValid_A	366540696	97630526	0	0
GrantKnown_A	366540696	365688664	0	0
IdxKnown_A	366540696	365688664	0	0
IndexIsCorrect_A	366540696	97630526	0	0
NoReadyValidNoGrant_A	366540696	42693245	0	0
Priority_A	366540696	103860393	0	0
ReadyAndValidImplyGrant_A	366540696	97630526	0	0
ReqAndReadyImplyGrant_A	366540696	97630526	0	0
ReqImpliesValid_A	366540696	103860393	0	0
ValidKnown_A	366540696	365688664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630526	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630526	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630526	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	42693245	0	0
T3	669	19	0	0
T4	4369	231	0	0
T5	335554	43387	0	0
T6	0	36	0	0
T7	0	36976	0	0
T8	0	7	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	157	0	0
T19	775	0	0	0
T22	0	62712	0	0
T24	789	0	0	0
T27	0	4	0	0
T48	0	70	0	0
T61	1654	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103860393	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	107882	0	0
T6	0	1167	0	0
T7	0	68958	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630526	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630526	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103860393	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	107882	0	0
T6	0	1167	0	0
T7	0	68958	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	366540696	365688664	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	366540696	97630648	0	0
GntImpliesValid_A	366540696	97630648	0	0
GrantKnown_A	366540696	365688664	0	0
IdxKnown_A	366540696	365688664	0	0
IndexIsCorrect_A	366540696	97630648	0	0
NoReadyValidNoGrant_A	366540696	42693211	0	0
Priority_A	366540696	103860549	0	0
ReadyAndValidImplyGrant_A	366540696	97630648	0	0
ReqAndReadyImplyGrant_A	366540696	97630648	0	0
ReqImpliesValid_A	366540696	103860549	0	0
ValidKnown_A	366540696	365688664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630648	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630648	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630648	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	42693211	0	0
T3	669	19	0	0
T4	4369	231	0	0
T5	335554	43387	0	0
T6	0	36	0	0
T7	0	36976	0	0
T8	0	7	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	157	0	0
T19	775	0	0	0
T22	0	62712	0	0
T24	789	0	0	0
T27	0	4	0	0
T48	0	70	0	0
T61	1654	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103860549	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	107882	0	0
T6	0	1167	0	0
T7	0	68958	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630648	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	97630648	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	94859	0	0
T6	0	1167	0	0
T7	0	57742	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	103860549	0	0
T3	669	7	0	0
T4	4369	102	0	0
T5	335554	107882	0	0
T6	0	1167	0	0
T7	0	68958	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	134420	0	0
T19	775	0	0	0
T20	0	276	0	0
T24	789	0	0	0
T26	0	682367	0	0
T27	0	1	0	0
T48	0	329528	0	0
T61	1654	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0