Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.80	100.00	91.19			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.63	100.00	90.53			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.69	100.00	90.75			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.63	100.00	90.53			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	99.17	93.43	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.06	100.00	92.45		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.69	100.00	90.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.64	99.17	93.51	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	454	414	91.19
Logical	454	414	91.19
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T106,T188
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T189
1	1	1	Covered	T57,T106,T188

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T28,T57,T190
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T28,T57,T190

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T27,T29,T57
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T27,T29,T57

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T190,T191
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T57,T190,T191

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T177,T180,T81
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Covered	T192
1	1	1	1	1	1	0	Covered	T5,T97,T56
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T30,T185,T193
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T7,T50
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T27,T30,T185
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T194,T195
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T30,T185,T99
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T56,T195
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T97
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T101
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T194
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T56
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T23
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T23
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T30

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T64
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T64

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T23

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T23
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T23

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T27

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T27,T33
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T27,T33

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T30

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T64
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T64

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T50
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T22
1	0	Covered	T16,T62
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T5,T27
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T22
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T196,T151,T152
1	1	0	1	1	1	Covered	T5,T7,T8
1	1	1	0	1	1	Covered	T54
1	1	1	1	0	1	Covered	T3,T4,T5
1	1	1	1	1	0	Covered	T7,T22,T50
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T20,T6
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T50

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T13

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T33,T135
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T135,T183

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T23

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T23,T41
1	0	Covered	T27,T135,T183

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T33,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T23,T41

 LINE       488
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T62
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T18,T24
1	1	0	Covered	T4,T8,T50
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T50,T45
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T4,T8,T50

 LINE       498
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T50,T97
1	1	1	Covered	T4,T5,T18

 LINE       500
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T50

 LINE       502
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       510
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       510
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       510
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T50

 LINE       518
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T97,T195
1	1	Covered	T4,T5,T18

 LINE       518
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T50

 LINE       520
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T50
1	1	0	Covered	T5,T18,T24
1	1	1	Covered	T1,T2,T3

 LINE       575
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       591
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T22,T50
1	1	0	Covered	T4,T8,T50
1	1	1	Covered	T1,T2,T3

 LINE       601
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       601
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       605
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       605
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       613
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18

 LINE       613
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       630
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       630
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T62
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       635
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T4,T5,T18

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       651
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T189
1	0	Not Covered

 LINE       657
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       670
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       691
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       691
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       703
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       706
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T27

 LINE       706
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T27

 LINE       706
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T135,T183,T57

 LINE       706
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T189

 LINE       710
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T27

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T27,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T8,T50
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	733081392	1632154	0	0
ExclusiveOps_A	733081392	731377328	0	0
ExclusiveProgHazard_A	733081392	731377328	0	0
ExclusiveState_A	733081392	731377328	0	0
ForwardCheck_A	733081392	3981135	0	0
IdleCheck_A	733081392	102249538	0	0
MaxBufs_A	2044	2044	0	0
OneHotAlloc_A	733081392	731377328	0	0
OneHotMatch_A	733081392	731377328	0	0
OneHotRspMatch_A	733081392	731377328	0	0
OneHotUpdate_A	733081392	731377328	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	1632154	0	0
T3	669	3	0	0
T4	8738	149	0	0
T5	671108	2692	0	0
T6	4789	23	0	0
T7	0	826	0	0
T9	3688	0	0	0
T13	1925492	0	0	0
T17	1058	0	0	0
T18	409190	74	0	0
T19	1550	0	0	0
T20	1874	5	0	0
T22	0	13313	0	0
T23	0	200	0	0
T24	1578	12	0	0
T27	0	31	0	0
T33	0	256	0	0
T48	0	77	0	0
T61	3308	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	3981135	0	0
T4	4369	9	0	0
T5	671108	37352	0	0
T6	9578	27	0	0
T7	0	85	0	0
T8	0	12	0	0
T9	3688	0	0	0
T13	1925492	0	0	0
T18	409190	34	0	0
T19	1550	0	0	0
T20	3748	6	0	0
T23	0	200	0	0
T24	1578	12	0	0
T33	0	3840	0	0
T39	0	16309	0	0
T48	0	41	0	0
T50	0	21126	0	0
T51	0	126	0	0
T61	3308	0	0	0
T65	996	0	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	102249538	0	0
T1	1144	268	0	0
T2	3529	583	0	0
T3	1338	147	0	0
T4	8738	875	0	0
T5	671108	142330	0	0
T6	0	36	0	0
T7	0	51548	0	0
T8	0	12	0	0
T9	3688	256	0	0
T13	1925492	192	0	0
T17	2116	128	0	0
T18	409190	494	0	0
T19	1550	128	0	0
T22	0	68151	0	0
T24	789	0	0	0
T27	0	4	0	0
T48	0	70	0	0
T61	1654	0	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2044	2044	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T13	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733081392	731377328	0	0
T1	2288	1844	0	0
T2	7058	5808	0	0
T3	1338	1190	0	0
T4	8738	8522	0	0
T5	671108	670998	0	0
T9	3688	3456	0	0
T13	1925492	1925162	0	0
T17	2116	1968	0	0
T18	409190	409074	0	0
T19	1550	1396	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	454	411	90.53
Logical	454	411	90.53
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T57,T188,T190
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T57,T188,T190

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T28,T57,T190
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T28,T57,T190

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T27,T29,T57
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T27,T29,T57

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T57,T190,T191
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T57,T190,T191

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T18
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T177,T180,T81
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T190,T191,T197
1	1	1	1	1	0	1	Covered	T192
1	1	1	1	1	1	0	Covered	T198,T199,T200
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T18
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T30,T185,T193
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T57,T190,T201
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T50,T56
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T18
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T27,T30,T185
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T57,T190,T201
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T194,T195,T119
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T18
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T30,T185,T99
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T195,T100
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T101,T198,T199
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T50
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T101,T194,T195
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T195
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T23
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T23
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T101,T50
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T23,T101
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T4,T5,T18
1	1	Covered	T18,T48,T30

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T64
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T64

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T4,T5,T18
1	1	Covered	T18,T48,T23

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T23
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T23

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T4,T5,T18
1	1	Covered	T18,T48,T27

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T27,T33
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T27,T33

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T18,T48
1	0	Covered	T4,T5,T18
1	1	Covered	T18,T48,T30

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T30
0	1	0	Covered	T13,T33,T64
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T9
1	1	Covered	T13,T33,T64

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T18
1	1	Covered	T33,T64,T30

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T50
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T22
1	0	Covered	T16,T62
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T5,T27
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T22
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T152
1	1	0	1	1	1	Covered	T5,T7,T8
1	1	1	0	1	1	Covered	T54
1	1	1	1	0	1	Covered	T4,T5,T18
1	1	1	1	1	0	Covered	T7,T22,T50
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T20,T6
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T50

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T13

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T33,T135
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T135,T183

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T23

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T23,T41
1	0	Covered	T27,T135,T183

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T33,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T23,T41

 LINE       488
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T62
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T18,T24
1	1	0	Covered	T4,T8,T50
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T50,T45
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T4,T8,T50

 LINE       498
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T50,T97
1	1	1	Covered	T4,T5,T18

 LINE       500
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T50

 LINE       502
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       510
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       510
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       510
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T50

 LINE       518
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T97,T195
1	1	Covered	T4,T5,T18

 LINE       518
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T50

 LINE       520
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T50
1	1	0	Covered	T5,T18,T24
1	1	1	Covered	T1,T2,T3

 LINE       575
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       591
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T22,T50
1	1	0	Covered	T4,T8,T50
1	1	1	Covered	T1,T2,T3

 LINE       601
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       601
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       605
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       605
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       613
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18

 LINE       613
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       630
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       630
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T62
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       635
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T4,T5,T18
1	1	1	1	Covered	T4,T5,T18

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T4,T5,T18
1	1	1	1	Covered	T4,T5,T18

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T4,T5,T18
1	1	1	1	Covered	T4,T5,T18

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T4,T5,T18
1	1	1	1	Covered	T4,T5,T18

 LINE       651
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Not Covered
1	0	Not Covered

 LINE       657
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       670
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       691
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       691
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       703
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3

 LINE       706
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T27

 LINE       706
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T27

 LINE       706
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T135,T183,T57

 LINE       706
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T18
1	1	Not Covered

 LINE       710
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T27

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T27,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T8,T50
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	366540696	851069	0	0
ExclusiveOps_A	366540696	365688664	0	0
ExclusiveProgHazard_A	366540696	365688664	0	0
ExclusiveState_A	366540696	365688664	0	0
ForwardCheck_A	366540696	2140197	0	0
IdleCheck_A	366540696	52686574	0	0
MaxBufs_A	1022	1022	0	0
OneHotAlloc_A	366540696	365688664	0	0
OneHotMatch_A	366540696	365688664	0	0
OneHotRspMatch_A	366540696	365688664	0	0
OneHotUpdate_A	366540696	365688664	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	851069	0	0
T4	4369	90	0	0
T5	335554	1322	0	0
T6	4789	13	0	0
T7	0	474	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T18	204595	45	0	0
T19	775	0	0	0
T20	1874	5	0	0
T22	0	6336	0	0
T24	789	12	0	0
T27	0	31	0	0
T48	0	59	0	0
T61	1654	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	2140197	0	0
T4	4369	9	0	0
T5	335554	15804	0	0
T6	4789	14	0	0
T7	0	85	0	0
T8	0	6	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T18	204595	28	0	0
T19	775	0	0	0
T20	1874	6	0	0
T24	789	12	0	0
T33	0	3072	0	0
T48	0	29	0	0
T61	1654	0	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	52686574	0	0
T1	1144	268	0	0
T2	3529	583	0	0
T3	669	128	0	0
T4	4369	644	0	0
T5	335554	78571	0	0
T9	1844	256	0	0
T13	962746	192	0	0
T17	1058	128	0	0
T18	204595	337	0	0
T19	775	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	454	412	90.75
Logical	454	412	90.75
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T106,T190
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T189
1	1	1	Covered	T57,T106,T190

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T190,T191
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T57,T190,T191

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T190,T191
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T57,T190,T191

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T57,T190,T191
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T57,T190,T191

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T113,T202,T203
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T201,T204
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T97,T56
1	1	1	1	1	1	1	Covered	T4,T5,T18

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T193,T102,T104
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T7,T97,T56
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T193,T102,T104
1	1	1	0	1	1	1	Covered	T3,T4,T5
1	1	1	1	0	1	1	Covered	T57,T190,T191
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T5,T205,T100
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T3,T4,T5
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T193,T102,T104
1	1	1	0	1	1	1	Covered	T4,T5,T18
1	1	1	1	0	1	1	Covered	T57,T191,T201
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T56,T100,T119
1	1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T97
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T101,T97
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T101,T205
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T101,T56,T100
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T101,T50
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T101
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T7,T101
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T48,T33
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T35

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T34
0	1	0	Covered	T33,T64,T34
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T33,T64,T34

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T48,T33
1	1	Covered	T33,T64,T34

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T48,T33
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T35

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T34
0	1	0	Covered	T33,T64,T34
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T33,T64,T34

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T48,T33
1	1	Covered	T33,T64,T34

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T48,T33
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T35

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T34
0	1	0	Covered	T33,T64,T34
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T33,T64,T34

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T48,T33
1	1	Covered	T33,T64,T34

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T48,T33
1	0	Covered	T3,T4,T5
1	1	Covered	T18,T48,T35

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T64,T34
0	1	0	Covered	T33,T64,T34
1	0	0	Covered	T18,T48,T33

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T33,T64,T34

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T48,T33
1	1	Covered	T33,T64,T34

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T50
1	1	Covered	T3,T4,T5

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T18,T20
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T22,T50
1	0	Covered	T16,T62
1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T27,T7
1	1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T7,T22,T50
1	1	1	Covered	T1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T18

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T196,T151
1	1	0	1	1	1	Covered	T5,T7,T8
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T3,T4,T5
1	1	1	1	1	0	Covered	T7,T22,T50
1	1	1	1	1	1	Covered	T3,T4,T5

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T18

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T18,T6,T48
1	1	Covered	T3,T4,T5

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T6
1	0	Covered	T3,T4,T5
1	1	Covered	T8,T50,T97

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T6

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T33,T39,T34
1	0	Covered	T3,T4,T5
1	1	Covered	T57,T106,T190

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T23,T41

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T23,T41
1	0	Covered	T57,T106,T190

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T33,T23
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T23,T41

 LINE       488
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T62
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T18
1	0	1	Covered	T5,T18,T6
1	1	0	Covered	T50,T97,T195
1	1	1	Covered	T3,T4,T18

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T98,T193
1	1	0	Covered	T3,T4,T18
1	1	1	Covered	T50,T97,T195

 LINE       498
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T18
1	1	0	Covered	T50,T97,T100
1	1	1	Covered	T5,T18,T6

 LINE       500
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T18,T6
1	1	Covered	T3,T4,T18

 LINE       501
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T50,T97,T195

 LINE       502
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T18
1	1	Covered	T5,T18,T6

 LINE       510
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T18

 LINE       510
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T18
1	1	Covered	T3,T4,T18

 LINE       510
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T50,T97,T195

 LINE       518
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T97,T195
1	1	Covered	T5,T18,T6

 LINE       518
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T50,T97,T195

 LINE       520
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T18

 LINE       574
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T50,T97
1	1	0	Covered	T5,T18,T6
1	1	1	Covered	T3,T4,T18

 LINE       575
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T33,T49
1	0	Covered	T3,T4,T18
1	1	Covered	T3,T4,T18

 LINE       591
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T22,T50
1	1	0	Covered	T50,T97,T195
1	1	1	Covered	T3,T4,T18

 LINE       601
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T6

 LINE       601
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T18

 LINE       605
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T6

 LINE       605
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T5,T18,T6
1	Covered	T1,T2,T3

 LINE       613
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T18
1	0	Covered	T5,T18,T6

 LINE       613
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T18

 LINE       630
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T6

 LINE       630
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T18

 LINE       630
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T18,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T18

 LINE       635
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T62
1	0	1	Covered	T33,T64,T34
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       635
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       635
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T4,T5,T18

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T3,T4,T5
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T18
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T3,T4,T5

 LINE       651
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T189
1	0	Not Covered

 LINE       657
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       670
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T56,T42,T57

 LINE       691
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       691
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T27

 LINE       703
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       706
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T56,T42,T57

 LINE       706
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Covered	T3,T4,T5
1	1	Covered	T56,T42,T57

 LINE       706
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T3,T4,T27
1	0	0	Covered	T57,T190,T191

 LINE       706
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T189

 LINE       710
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Covered	T3,T4,T5
1	1	Covered	T56,T42,T57

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T18
0	1	Covered	T50,T97,T195
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T18,T6
0	1	Covered	T3,T4,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T18,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T18,T6

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T18,T6
0	1	Covered	T3,T4,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T56,T42,T57
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T18
0	0	1	Covered	T3,T4,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	366540696	781085	0	0
ExclusiveOps_A	366540696	365688664	0	0
ExclusiveProgHazard_A	366540696	365688664	0	0
ExclusiveState_A	366540696	365688664	0	0
ForwardCheck_A	366540696	1840938	0	0
IdleCheck_A	366540696	49562964	0	0
MaxBufs_A	1022	1022	0	0
OneHotAlloc_A	366540696	365688664	0	0
OneHotMatch_A	366540696	365688664	0	0
OneHotRspMatch_A	366540696	365688664	0	0
OneHotUpdate_A	366540696	365688664	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	781085	0	0
T3	669	3	0	0
T4	4369	59	0	0
T5	335554	1370	0	0
T6	0	10	0	0
T7	0	352	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	29	0	0
T19	775	0	0	0
T22	0	6977	0	0
T23	0	200	0	0
T24	789	0	0	0
T33	0	256	0	0
T48	0	18	0	0
T61	1654	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	1840938	0	0
T5	335554	21548	0	0
T6	4789	13	0	0
T8	0	6	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T18	204595	6	0	0
T19	775	0	0	0
T20	1874	0	0	0
T23	0	200	0	0
T24	789	0	0	0
T33	0	768	0	0
T39	0	16309	0	0
T48	0	12	0	0
T50	0	21126	0	0
T51	0	126	0	0
T61	1654	0	0	0
T65	996	0	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	49562964	0	0
T3	669	19	0	0
T4	4369	231	0	0
T5	335554	63759	0	0
T6	0	36	0	0
T7	0	51548	0	0
T8	0	12	0	0
T9	1844	0	0	0
T13	962746	0	0	0
T17	1058	0	0	0
T18	204595	157	0	0
T19	775	0	0	0
T22	0	68151	0	0
T24	789	0	0	0
T27	0	4	0	0
T48	0	70	0	0
T61	1654	0	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366540696	365688664	0	0
T1	1144	922	0	0
T2	3529	2904	0	0
T3	669	595	0	0
T4	4369	4261	0	0
T5	335554	335499	0	0
T9	1844	1728	0	0
T13	962746	962581	0	0
T17	1058	984	0	0
T18	204595	204537	0	0
T19	775	698	0	0