Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25230535	1		T1	100		T2	72		T3	794
full_word	7843014	1		T1	118		T2	47		T3	233

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33073269	1		T1	218		T2	119		T3	1027
auto[TlIntgErrCmd]	100	1		T70	7		T186	1		T219	9
auto[TlIntgErrData]	89	1		T70	10		T186	7		T219	4
auto[TlIntgErrBoth]	91	1		T70	3		T186	2		T219	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28481304	1		T1	89		T2	67		T3	820
auto[1]	4592245	1		T1	129		T2	52		T3	207

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24473146	1		T1	84		T2	67		T3	771
auto[TlIntgErrNone]	partial	auto[1]	757133	1		T1	16		T2	5		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	4008037	1		T1	5		T3	49		T18	1
auto[TlIntgErrNone]	full_word	auto[1]	3834953	1		T1	113		T2	47		T3	184
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T70	4		T186	1		T219	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T70	2		T219	5		T228	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T70	1		T344	1		T294	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T219	1		T228	1		T294	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T70	3		T186	2		T219	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T70	7		T186	5		T219	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T229	1		T344	1		T347	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T229	1		T345	1		T349	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T70	1		T186	2		T219	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T70	2		T219	3		T228	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T344	1		T349	1		T350	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T219	1		T228	1		T348	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18497	1		T70	16		T186	8		T187	195
full_word	4255156	1		T3	90		T21	568		T5	41473

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4273390	1		T3	90		T21	568		T5	41473
auto[TlIntgErrCmd]	83	1		T70	8		T219	8		T228	3
auto[TlIntgErrData]	84	1		T70	4		T186	5		T219	6
auto[TlIntgErrBoth]	96	1		T70	8		T186	5		T219	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4249753	1		T3	90		T21	568		T5	41473
auto[1]	23900	1		T70	14		T186	6		T187	228

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1251	1		T187	15		T217	37		T218	10
auto[TlIntgErrNone]	partial	auto[1]	17006	1		T187	180		T217	611		T218	116
auto[TlIntgErrNone]	full_word	auto[0]	4248405	1		T3	90		T21	568		T5	41473
auto[TlIntgErrNone]	full_word	auto[1]	6728	1		T187	48		T217	122		T218	84
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T70	3		T219	2		T229	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T70	4		T219	6		T228	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T228	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T70	1		T228	1		T229	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T70	2		T186	3		T219	2
auto[TlIntgErrData]	partial	auto[1]	39	1		T70	2		T186	1		T219	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T219	1		T299	1		T351	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T186	1		T219	1		T348	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T70	1		T186	1		T228	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T70	4		T186	3		T219	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T229	1		T344	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T70	3		T186	1		T229	1