Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1580129404	1576904532	0	0
CheckNGreaterZero_A	4132	4132	0	0
GntImpliesReady_A	1580129404	410666097	0	0
GntImpliesValid_A	1580129404	410666097	0	0
GrantKnown_A	1580129404	1576904532	0	0
IdxKnown_A	1580129404	1576904532	0	0
IndexIsCorrect_A	1580129404	410666097	0	0
NoReadyValidNoGrant_A	1580129404	183412869	0	0
Priority_A	1580129404	434842282	0	0
ReadyAndValidImplyGrant_A	1580129404	410666097	0	0
ReqAndReadyImplyGrant_A	1580129404	410666097	0	0
ReqImpliesValid_A	1580129404	434842282	0	0
ValidKnown_A	1580129404	1576904532	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	1576904532	0	0
T1	12680	12428	0	0
T2	5516	5000	0	0
T3	14084	13704	0	0
T4	688296	688072	0	0
T10	14800	11652	0	0
T17	17484	17272	0	0
T18	5988	5732	0	0
T19	6216	5936	0	0
T20	1927168	1926412	0	0
T21	133836	133512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4132	4132	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	410666097	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3078	0	0
T4	688296	53314	0	0
T5	0	190262	0	0
T6	0	19188	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	410666097	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3078	0	0
T4	688296	53314	0	0
T5	0	190262	0	0
T6	0	19188	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	1576904532	0	0
T1	12680	12428	0	0
T2	5516	5000	0	0
T3	14084	13704	0	0
T4	688296	688072	0	0
T10	14800	11652	0	0
T17	17484	17272	0	0
T18	5988	5732	0	0
T19	6216	5936	0	0
T20	1927168	1926412	0	0
T21	133836	133512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	1576904532	0	0
T1	12680	12428	0	0
T2	5516	5000	0	0
T3	14084	13704	0	0
T4	688296	688072	0	0
T10	14800	11652	0	0
T17	17484	17272	0	0
T18	5988	5732	0	0
T19	6216	5936	0	0
T20	1927168	1926412	0	0
T21	133836	133512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	410666097	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3078	0	0
T4	688296	53314	0	0
T5	0	190262	0	0
T6	0	19188	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	183412869	0	0
T1	12680	264	0	0
T2	5516	512	0	0
T3	14084	496	0	0
T4	688296	128	0	0
T5	0	91812	0	0
T6	0	23916	0	0
T10	14800	1628	0	0
T17	17484	256	0	0
T18	5988	256	0	0
T19	6216	256	0	0
T20	1927168	365536	0	0
T21	133836	4936	0	0
T22	0	806400	0	0
T23	0	552	0	0
T25	0	194	0	0
T28	0	51724	0	0
T60	0	4116	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	434842282	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3084	0	0
T4	688296	53314	0	0
T5	0	242844	0	0
T6	0	24940	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	410666097	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3078	0	0
T4	688296	53314	0	0
T5	0	190262	0	0
T6	0	19188	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	410666097	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3078	0	0
T4	688296	53314	0	0
T5	0	190262	0	0
T6	0	19188	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	434842282	0	0
T1	12680	1350	0	0
T2	5516	176	0	0
T3	14084	3084	0	0
T4	688296	53314	0	0
T5	0	242844	0	0
T6	0	24940	0	0
T10	14800	432	0	0
T17	17484	64	0	0
T18	5988	64	0	0
T19	6216	64	0	0
T20	1927168	276278	0	0
T21	133836	47030	0	0
T22	0	700710	0	0
T65	0	20568	0	0
T66	0	520	0	0
T67	0	200964	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580129404	1576904532	0	0
T1	12680	12428	0	0
T2	5516	5000	0	0
T3	14084	13704	0	0
T4	688296	688072	0	0
T10	14800	11652	0	0
T17	17484	17272	0	0
T18	5988	5732	0	0
T19	6216	5936	0	0
T20	1927168	1926412	0	0
T21	133836	133512	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395032351	394226133	0	0
CheckNGreaterZero_A	1033	1033	0	0
GntImpliesReady_A	395032351	104516579	0	0
GntImpliesValid_A	395032351	104516579	0	0
GrantKnown_A	395032351	394226133	0	0
IdxKnown_A	395032351	394226133	0	0
IndexIsCorrect_A	395032351	104516579	0	0
NoReadyValidNoGrant_A	395032351	47784744	0	0
Priority_A	395032351	110547801	0	0
ReadyAndValidImplyGrant_A	395032351	104516579	0	0
ReqAndReadyImplyGrant_A	395032351	104516579	0	0
ReqImpliesValid_A	395032351	110547801	0	0
ValidKnown_A	395032351	394226133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516579	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516579	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516579	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	47784744	0	0
T1	3170	128	0	0
T2	1379	256	0	0
T3	3521	183	0	0
T4	172074	64	0	0
T10	3700	814	0	0
T17	4371	128	0	0
T18	1497	128	0	0
T19	1554	128	0	0
T20	481792	182768	0	0
T21	33459	1568	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	110547801	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	755	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516579	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516579	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	110547801	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	755	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395032351	394226133	0	0
CheckNGreaterZero_A	1033	1033	0	0
GntImpliesReady_A	395032351	104516517	0	0
GntImpliesValid_A	395032351	104516517	0	0
GrantKnown_A	395032351	394226133	0	0
IdxKnown_A	395032351	394226133	0	0
IndexIsCorrect_A	395032351	104516517	0	0
NoReadyValidNoGrant_A	395032351	47784744	0	0
Priority_A	395032351	110547739	0	0
ReadyAndValidImplyGrant_A	395032351	104516517	0	0
ReqAndReadyImplyGrant_A	395032351	104516517	0	0
ReqImpliesValid_A	395032351	110547739	0	0
ValidKnown_A	395032351	394226133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516517	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516517	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516517	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	47784744	0	0
T1	3170	128	0	0
T2	1379	256	0	0
T3	3521	183	0	0
T4	172074	64	0	0
T10	3700	814	0	0
T17	4371	128	0	0
T18	1497	128	0	0
T19	1554	128	0	0
T20	481792	182768	0	0
T21	33459	1568	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	110547739	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	755	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516517	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	104516517	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	752	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	110547739	0	0
T1	3170	245	0	0
T2	1379	64	0	0
T3	3521	755	0	0
T4	172074	26657	0	0
T10	3700	216	0	0
T17	4371	32	0	0
T18	1497	32	0	0
T19	1554	32	0	0
T20	481792	138139	0	0
T21	33459	14487	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T25
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395032351	394226133	0	0
CheckNGreaterZero_A	1033	1033	0	0
GntImpliesReady_A	395032351	100816512	0	0
GntImpliesValid_A	395032351	100816512	0	0
GrantKnown_A	395032351	394226133	0	0
IdxKnown_A	395032351	394226133	0	0
IndexIsCorrect_A	395032351	100816512	0	0
NoReadyValidNoGrant_A	395032351	43921713	0	0
Priority_A	395032351	106873360	0	0
ReadyAndValidImplyGrant_A	395032351	100816512	0	0
ReqAndReadyImplyGrant_A	395032351	100816512	0	0
ReqImpliesValid_A	395032351	106873360	0	0
ValidKnown_A	395032351	394226133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816512	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816512	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816512	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	43921713	0	0
T1	3170	4	0	0
T2	1379	0	0	0
T3	3521	65	0	0
T4	172074	0	0	0
T5	0	45906	0	0
T6	0	11958	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	900	0	0
T22	0	403200	0	0
T23	0	276	0	0
T25	0	97	0	0
T28	0	25862	0	0
T60	0	2058	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	106873360	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	121422	0	0
T6	0	12470	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816512	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816512	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	106873360	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	121422	0	0
T6	0	12470	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T25
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T21,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395032351	394226133	0	0
CheckNGreaterZero_A	1033	1033	0	0
GntImpliesReady_A	395032351	100816489	0	0
GntImpliesValid_A	395032351	100816489	0	0
GrantKnown_A	395032351	394226133	0	0
IdxKnown_A	395032351	394226133	0	0
IndexIsCorrect_A	395032351	100816489	0	0
NoReadyValidNoGrant_A	395032351	43921668	0	0
Priority_A	395032351	106873382	0	0
ReadyAndValidImplyGrant_A	395032351	100816489	0	0
ReqAndReadyImplyGrant_A	395032351	100816489	0	0
ReqImpliesValid_A	395032351	106873382	0	0
ValidKnown_A	395032351	394226133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816489	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816489	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816489	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	43921668	0	0
T1	3170	4	0	0
T2	1379	0	0	0
T3	3521	65	0	0
T4	172074	0	0	0
T5	0	45906	0	0
T6	0	11958	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	900	0	0
T22	0	403200	0	0
T23	0	276	0	0
T25	0	97	0	0
T28	0	25862	0	0
T60	0	2058	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	106873382	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	121422	0	0
T6	0	12470	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816489	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	100816489	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	95131	0	0
T6	0	9594	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	106873382	0	0
T1	3170	430	0	0
T2	1379	24	0	0
T3	3521	787	0	0
T4	172074	0	0	0
T5	0	121422	0	0
T6	0	12470	0	0
T10	3700	0	0	0
T17	4371	0	0	0
T18	1497	0	0	0
T19	1554	0	0	0
T20	481792	0	0	0
T21	33459	9028	0	0
T22	0	350355	0	0
T65	0	10284	0	0
T66	0	260	0	0
T67	0	100482	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395032351	394226133	0	0
T1	3170	3107	0	0
T2	1379	1250	0	0
T3	3521	3426	0	0
T4	172074	172018	0	0
T10	3700	2913	0	0
T17	4371	4318	0	0
T18	1497	1433	0	0
T19	1554	1484	0	0
T20	481792	481603	0	0
T21	33459	33378	0	0