Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 27473247 1 T1 174195 T2 57 T3 504
full_word 8015570 1 T1 26046 T2 1 T3 1


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 35488537 1 T1 200241 T2 58 T3 505
auto[TlIntgErrCmd] 105 1 T216 5 T248 6 T249 4
auto[TlIntgErrData] 95 1 T216 7 T248 5 T249 3
auto[TlIntgErrBoth] 80 1 T216 8 T248 9 T249 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30865185 1 T1 179956 T2 57 T3 497
auto[1] 4623632 1 T1 20285 T2 1 T3 8


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 26715255 1 T1 171618 T2 57 T3 497
auto[TlIntgErrNone] partial auto[1] 757747 1 T1 2577 T3 7 T4 286
auto[TlIntgErrNone] full_word auto[0] 4149802 1 T1 8338 T4 3783 T5 180
auto[TlIntgErrNone] full_word auto[1] 3865733 1 T1 17708 T2 1 T3 1
auto[TlIntgErrCmd] partial auto[0] 41 1 T248 3 T249 3 T297 1
auto[TlIntgErrCmd] partial auto[1] 50 1 T216 5 T248 2 T249 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T265 1 T355 1 T354 1
auto[TlIntgErrCmd] full_word auto[1] 11 1 T248 1 T350 1 T263 3
auto[TlIntgErrData] partial auto[0] 50 1 T216 1 T248 3 T249 1
auto[TlIntgErrData] partial auto[1] 34 1 T216 6 T249 2 T297 2
auto[TlIntgErrData] full_word auto[0] 6 1 T248 1 T350 2 T355 1
auto[TlIntgErrData] full_word auto[1] 5 1 T248 1 T349 1 T264 1
auto[TlIntgErrBoth] partial auto[0] 23 1 T216 3 T248 3 T249 1
auto[TlIntgErrBoth] partial auto[1] 47 1 T216 5 T248 4 T249 2
auto[TlIntgErrBoth] full_word auto[0] 5 1 T264 1 T265 2 T356 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T248 2 T263 1 T357 2


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 18302 1 T182 746 T183 1412 T65 20
full_word 4134428 1 T1 41562 T5 24 T12 9


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4152465 1 T1 41562 T5 24 T12 9
auto[TlIntgErrCmd] 92 1 T216 13 T248 4 T249 5
auto[TlIntgErrData] 90 1 T216 2 T248 9 T249 2
auto[TlIntgErrBoth] 83 1 T216 5 T248 6 T249 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4129118 1 T1 41562 T5 24 T12 9
auto[1] 23612 1 T182 953 T183 1813 T65 37


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1234 1 T182 65 T183 88 T65 2
auto[TlIntgErrNone] partial auto[1] 16828 1 T182 681 T183 1324 T65 18
auto[TlIntgErrNone] full_word auto[0] 4127783 1 T1 41562 T5 24 T12 9
auto[TlIntgErrNone] full_word auto[1] 6620 1 T182 272 T183 489 T65 19
auto[TlIntgErrCmd] partial auto[0] 26 1 T216 4 T248 1 T249 2
auto[TlIntgErrCmd] partial auto[1] 56 1 T216 7 T248 3 T249 3
auto[TlIntgErrCmd] full_word auto[0] 4 1 T216 1 T297 1 T358 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T216 1 T297 1 T350 1
auto[TlIntgErrData] partial auto[0] 40 1 T216 2 T248 5 T297 3
auto[TlIntgErrData] partial auto[1] 41 1 T248 2 T249 2 T349 2
auto[TlIntgErrData] full_word auto[0] 3 1 T248 1 T354 1 T357 1
auto[TlIntgErrData] full_word auto[1] 6 1 T248 1 T264 1 T265 1
auto[TlIntgErrBoth] partial auto[0] 26 1 T216 2 T248 2 T249 1
auto[TlIntgErrBoth] partial auto[1] 51 1 T216 3 T248 4 T249 2
auto[TlIntgErrBoth] full_word auto[0] 2 1 T349 1 T264 1 - -
auto[TlIntgErrBoth] full_word auto[1] 4 1 T350 1 T354 2 T348 1

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