Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24933755	1		T1	82269		T2	12130		T3	144
full_word	7524151	1		T1	10612		T2	8979		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32457616	1		T1	92881		T2	21109		T3	148
auto[TlIntgErrCmd]	85	1		T69	6		T216	2		T286	4
auto[TlIntgErrData]	98	1		T69	5		T216	3		T286	3
auto[TlIntgErrBoth]	107	1		T69	9		T216	5		T286	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28114760	1		T1	81864		T2	17800		T3	139
auto[1]	4343146	1		T1	11017		T2	3309		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24321776	1		T1	81087		T2	11201		T3	139
auto[TlIntgErrNone]	partial	auto[1]	611711	1		T1	1182		T2	929		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	3792839	1		T1	777		T2	6599		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	3731290	1		T1	9835		T2	2380		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T69	3		T216	1		T286	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T69	3		T286	3		T247	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T400	1		T304	1		T401	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T216	1		T394	1		T294	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T69	2		T216	1		T286	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T69	2		T216	1		T247	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T302	1		T294	1		T402	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T69	1		T216	1		T396	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1		T69	4		T216	4		T286	3
auto[TlIntgErrBoth]	partial	auto[1]	42	1		T69	2		T216	1		T247	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T398	1		T403	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T69	3		T394	1		T301	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22254	1		T69	18		T71	161		T217	789
full_word	3991645	1		T2	15040		T5	40989		T6	16243

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4013637	1		T2	15040		T5	40989		T6	16243
auto[TlIntgErrCmd]	84	1		T69	4		T216	4		T286	1
auto[TlIntgErrData]	98	1		T69	10		T216	3		T286	7
auto[TlIntgErrBoth]	80	1		T69	5		T216	2		T286	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3986695	1		T2	15040		T5	40989		T6	16243
auto[1]	27204	1		T69	8		T71	188		T217	907

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1408	1		T71	8		T217	34		T245	4
auto[TlIntgErrNone]	partial	auto[1]	20608	1		T71	153		T217	755		T245	93
auto[TlIntgErrNone]	full_word	auto[0]	3985179	1		T2	15040		T5	40989		T6	16243
auto[TlIntgErrNone]	full_word	auto[1]	6442	1		T71	35		T217	152		T245	33
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T69	1		T216	1		T286	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T69	3		T216	3		T297	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T402	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T247	1		T399	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1		T69	7		T216	3		T286	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T69	2		T286	4		T247	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T69	1		T247	1		T297	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T286	1		T400	1		T294	1
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T69	2		T297	1		T301	6
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T69	3		T216	1		T286	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T297	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T216	1		T247	1		T297	1