Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1581336924	1578154528	0	0
CheckNGreaterZero_A	4120	4120	0	0
GntImpliesReady_A	1581336924	413180395	0	0
GntImpliesValid_A	1581336924	413180395	0	0
GrantKnown_A	1581336924	1578154528	0	0
IdxKnown_A	1581336924	1578154528	0	0
IndexIsCorrect_A	1581336924	413180395	0	0
NoReadyValidNoGrant_A	1581336924	171527558	0	0
Priority_A	1581336924	437644001	0	0
ReadyAndValidImplyGrant_A	1581336924	413180395	0	0
ReqAndReadyImplyGrant_A	1581336924	413180395	0	0
ReqImpliesValid_A	1581336924	437644001	0	0
ValidKnown_A	1581336924	1578154528	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	1578154528	0	0
T1	746940	746604	0	0
T2	190928	190684	0	0
T3	14736	12084	0	0
T4	7200	6616	0	0
T5	1349728	1349512	0	0
T6	252900	252672	0	0
T10	5976	5152	0	0
T14	5412	5176	0	0
T15	6872	6552	0	0
T16	17052	16736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4120	4120	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	413180395	0	0
T1	746940	321700	0	0
T2	190928	40202	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	393842	0	0
T6	252900	43668	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	52312	0	0
T28	0	16288	0	0
T40	0	1220	0	0
T42	0	213430	0	0
T49	0	55910	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	413180395	0	0
T1	746940	321700	0	0
T2	190928	40202	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	393842	0	0
T6	252900	43668	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	52312	0	0
T28	0	16288	0	0
T40	0	1220	0	0
T42	0	213430	0	0
T49	0	55910	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	1578154528	0	0
T1	746940	746604	0	0
T2	190928	190684	0	0
T3	14736	12084	0	0
T4	7200	6616	0	0
T5	1349728	1349512	0	0
T6	252900	252672	0	0
T10	5976	5152	0	0
T14	5412	5176	0	0
T15	6872	6552	0	0
T16	17052	16736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	1578154528	0	0
T1	746940	746604	0	0
T2	190928	190684	0	0
T3	14736	12084	0	0
T4	7200	6616	0	0
T5	1349728	1349512	0	0
T6	252900	252672	0	0
T10	5976	5152	0	0
T14	5412	5176	0	0
T15	6872	6552	0	0
T16	17052	16736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	413180395	0	0
T1	746940	321700	0	0
T2	190928	40202	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	393842	0	0
T6	252900	43668	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	52312	0	0
T28	0	16288	0	0
T40	0	1220	0	0
T42	0	213430	0	0
T49	0	55910	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	171527558	0	0
T1	373470	256	0	0
T2	190928	68468	0	0
T3	14736	1568	0	0
T4	7200	512	0	0
T5	1349728	316760	0	0
T6	252900	125520	0	0
T10	5976	536	0	0
T14	5412	256	0	0
T15	6872	316	0	0
T16	17052	256	0	0
T21	0	1048576	0	0
T25	0	1573966	0	0
T28	0	19884	0	0
T29	0	50062	0	0
T40	0	20	0	0
T42	0	76060	0	0
T49	325986	3660	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	437644001	0	0
T1	746940	321700	0	0
T2	190928	48974	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	458134	0	0
T6	252900	46206	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	314238	0	0
T28	0	21244	0	0
T40	0	1220	0	0
T42	0	267672	0	0
T49	0	55910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	413180395	0	0
T1	746940	321700	0	0
T2	190928	40202	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	393842	0	0
T6	252900	43668	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	52312	0	0
T28	0	16288	0	0
T40	0	1220	0	0
T42	0	213430	0	0
T49	0	55910	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	413180395	0	0
T1	746940	321700	0	0
T2	190928	40202	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	393842	0	0
T6	252900	43668	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	52312	0	0
T28	0	16288	0	0
T40	0	1220	0	0
T42	0	213430	0	0
T49	0	55910	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	437644001	0	0
T1	746940	321700	0	0
T2	190928	48974	0	0
T3	14736	440	0	0
T4	7200	138	0	0
T5	1349728	458134	0	0
T6	252900	46206	0	0
T10	5976	134	0	0
T14	5412	64	0	0
T15	6872	1178	0	0
T16	17052	64	0	0
T25	0	314238	0	0
T28	0	21244	0	0
T40	0	1220	0	0
T42	0	267672	0	0
T49	0	55910	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581336924	1578154528	0	0
T1	746940	746604	0	0
T2	190928	190684	0	0
T3	14736	12084	0	0
T4	7200	6616	0	0
T5	1349728	1349512	0	0
T6	252900	252672	0	0
T10	5976	5152	0	0
T14	5412	5176	0	0
T15	6872	6552	0	0
T16	17052	16736	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395334231	394538632	0	0
CheckNGreaterZero_A	1030	1030	0	0
GntImpliesReady_A	395334231	106179971	0	0
GntImpliesValid_A	395334231	106179971	0	0
GrantKnown_A	395334231	394538632	0	0
IdxKnown_A	395334231	394538632	0	0
IndexIsCorrect_A	395334231	106179971	0	0
NoReadyValidNoGrant_A	395334231	44128909	0	0
Priority_A	395334231	112361717	0	0
ReadyAndValidImplyGrant_A	395334231	106179971	0	0
ReqAndReadyImplyGrant_A	395334231	106179971	0	0
ReqImpliesValid_A	395334231	112361717	0	0
ValidKnown_A	395334231	394538632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	44128909	0	0
T1	186735	128	0	0
T2	47732	19907	0	0
T3	3684	784	0	0
T4	1800	256	0	0
T5	337432	86386	0	0
T6	63225	32706	0	0
T10	1494	268	0	0
T14	1353	128	0	0
T15	1718	158	0	0
T16	4263	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	112361717	0	0
T1	186735	106904	0	0
T2	47732	11899	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	151047	0	0
T6	63225	12339	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	112361717	0	0
T1	186735	106904	0	0
T2	47732	11899	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	151047	0	0
T6	63225	12339	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395334231	394538632	0	0
CheckNGreaterZero_A	1030	1030	0	0
GntImpliesReady_A	395334231	106179971	0	0
GntImpliesValid_A	395334231	106179971	0	0
GrantKnown_A	395334231	394538632	0	0
IdxKnown_A	395334231	394538632	0	0
IndexIsCorrect_A	395334231	106179971	0	0
NoReadyValidNoGrant_A	395334231	44128909	0	0
Priority_A	395334231	112361717	0	0
ReadyAndValidImplyGrant_A	395334231	106179971	0	0
ReqAndReadyImplyGrant_A	395334231	106179971	0	0
ReqImpliesValid_A	395334231	112361717	0	0
ValidKnown_A	395334231	394538632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	44128909	0	0
T1	186735	128	0	0
T2	47732	19907	0	0
T3	3684	784	0	0
T4	1800	256	0	0
T5	337432	86386	0	0
T6	63225	32706	0	0
T10	1494	268	0	0
T14	1353	128	0	0
T15	1718	158	0	0
T16	4263	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	112361717	0	0
T1	186735	106904	0	0
T2	47732	11899	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	151047	0	0
T6	63225	12339	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106179971	0	0
T1	186735	106904	0	0
T2	47732	9870	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	126245	0	0
T6	63225	11648	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	112361717	0	0
T1	186735	106904	0	0
T2	47732	11899	0	0
T3	3684	220	0	0
T4	1800	64	0	0
T5	337432	151047	0	0
T6	63225	12339	0	0
T10	1494	67	0	0
T14	1353	32	0	0
T15	1718	589	0	0
T16	4263	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395334231	394538632	0	0
CheckNGreaterZero_A	1030	1030	0	0
GntImpliesReady_A	395334231	100410263	0	0
GntImpliesValid_A	395334231	100410263	0	0
GrantKnown_A	395334231	394538632	0	0
IdxKnown_A	395334231	394538632	0	0
IndexIsCorrect_A	395334231	100410263	0	0
NoReadyValidNoGrant_A	395334231	41634870	0	0
Priority_A	395334231	106460320	0	0
ReadyAndValidImplyGrant_A	395334231	100410263	0	0
ReqAndReadyImplyGrant_A	395334231	100410263	0	0
ReqImpliesValid_A	395334231	106460320	0	0
ValidKnown_A	395334231	394538632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410263	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410263	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410263	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	41634870	0	0
T2	47732	14327	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	71994	0	0
T6	63225	30054	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T21	0	524288	0	0
T25	0	786983	0	0
T28	0	9942	0	0
T29	0	25031	0	0
T40	0	10	0	0
T42	0	38030	0	0
T49	162993	1830	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106460320	0	0
T1	186735	53946	0	0
T2	47732	12588	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	78020	0	0
T6	63225	10764	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	157119	0	0
T28	0	10622	0	0
T40	0	610	0	0
T42	0	133836	0	0
T49	0	27955	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410263	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410263	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106460320	0	0
T1	186735	53946	0	0
T2	47732	12588	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	78020	0	0
T6	63225	10764	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	157119	0	0
T28	0	10622	0	0
T40	0	610	0	0
T42	0	133836	0	0
T49	0	27955	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395334231	394538632	0	0
CheckNGreaterZero_A	1030	1030	0	0
GntImpliesReady_A	395334231	100410190	0	0
GntImpliesValid_A	395334231	100410190	0	0
GrantKnown_A	395334231	394538632	0	0
IdxKnown_A	395334231	394538632	0	0
IndexIsCorrect_A	395334231	100410190	0	0
NoReadyValidNoGrant_A	395334231	41634870	0	0
Priority_A	395334231	106460247	0	0
ReadyAndValidImplyGrant_A	395334231	100410190	0	0
ReqAndReadyImplyGrant_A	395334231	100410190	0	0
ReqImpliesValid_A	395334231	106460247	0	0
ValidKnown_A	395334231	394538632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410190	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410190	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410190	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	41634870	0	0
T2	47732	14327	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	71994	0	0
T6	63225	30054	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T21	0	524288	0	0
T25	0	786983	0	0
T28	0	9942	0	0
T29	0	25031	0	0
T40	0	10	0	0
T42	0	38030	0	0
T49	162993	1830	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106460247	0	0
T1	186735	53946	0	0
T2	47732	12588	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	78020	0	0
T6	63225	10764	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	157119	0	0
T28	0	10622	0	0
T40	0	610	0	0
T42	0	133836	0	0
T49	0	27955	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410190	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	100410190	0	0
T1	186735	53946	0	0
T2	47732	10231	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	70676	0	0
T6	63225	10186	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	26156	0	0
T28	0	8144	0	0
T40	0	610	0	0
T42	0	106715	0	0
T49	0	27955	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	106460247	0	0
T1	186735	53946	0	0
T2	47732	12588	0	0
T3	3684	0	0	0
T4	1800	5	0	0
T5	337432	78020	0	0
T6	63225	10764	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	157119	0	0
T28	0	10622	0	0
T40	0	610	0	0
T42	0	133836	0	0
T49	0	27955	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0