Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.68	100.00	90.57		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T166,T281
1	0	Covered	T7,T166,T281

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T166,T281

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T282
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T166,T281
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T21,T104

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T40,T104,T41

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T104,T41

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T4,T5
1	1	Covered	T40,T104,T41

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T104,T41

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T15,T49,T40
1	Covered	T1,T4,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T1,T5,T15

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T1,T5,T15

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T5,T15

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T5,T42
StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc	215	Covered	T1,T4,T5
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T5
StPostPack	218	Covered	T40,T104,T41
StPrePack	195	Covered	T40,T104,T41
StReqFlash	237	Covered	T1,T5,T15
StScrambleData	244	Covered	T1,T5,T42
StWaitFlash	270	Covered	T1,T5,T15

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T5,T42
StCalcMask->StScrambleData	244	Covered	T1,T5,T42
StCalcPlainEcc->StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc->StReqFlash	237	Covered	T15,T49,T40
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T1,T4,T5
StIdle->StPrePack	195	Covered	T40,T104,T41
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T5
StPackData->StPostPack	218	Covered	T40,T104,T41
StPostPack->StCalcPlainEcc	231	Covered	T40,T104,T41
StPrePack->StPackData	205	Covered	T40,T104,T41
StReqFlash->StIdle	273	Covered	T1,T5,T15
StReqFlash->StWaitFlash	270	Covered	T1,T5,T15
StScrambleData->StCalcEcc	252	Covered	T1,T5,T42
StWaitFlash->StIdle	280	Covered	T1,T5,T15

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T41
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T41
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T41
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T40,T104,T41
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T15,T49,T40
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T5,T42
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T5,T42
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T5,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T15
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T12,T13

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T5,T15
0	0	1	-	-	Covered	T1,T5,T42
0	0	0	1	-	Covered	T1,T5,T42
0	0	0	0	1	Covered	T1,T4,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	790668462	2439572	0	0
PostPackRule_A	790668462	1999	0	0
PrePackRule_A	790668462	1418	0	0
WidthCheck_A	2060	2060	0	0
u_state_regs_A	790668462	789077264	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	2439572	0	0
T1	373470	1337	0	0
T2	95464	0	0	0
T3	7368	0	0	0
T4	3600	0	0	0
T5	674864	1381	0	0
T6	126450	0	0	0
T10	2988	0	0	0
T14	2706	0	0	0
T15	3436	1	0	0
T16	8526	0	0	0
T17	0	184	0	0
T21	0	65920	0	0
T26	0	1	0	0
T40	0	6	0	0
T41	0	12	0	0
T42	0	1527	0	0
T49	0	100	0	0
T50	0	309	0	0
T59	0	1	0	0
T60	0	169	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	1999	0	0
T11	7218	0	0	0
T17	306264	0	0	0
T18	1716	0	0	0
T21	786854	0	0	0
T23	0	7	0	0
T25	256852	0	0	0
T28	144206	0	0	0
T29	148452	0	0	0
T39	0	51	0	0
T40	6438	5	0	0
T41	0	7	0	0
T48	0	1	0	0
T50	139500	0	0	0
T51	1151620	0	0	0
T55	0	1	0	0
T78	0	5	0	0
T104	0	2	0	0
T137	0	1	0	0
T173	0	32	0	0
T189	0	31	0	0
T195	0	2	0	0
T283	0	1	0	0
T284	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	1418	0	0
T11	7218	0	0	0
T17	306264	0	0	0
T18	1716	0	0	0
T21	786854	0	0	0
T23	0	5	0	0
T25	256852	0	0	0
T28	144206	0	0	0
T29	148452	0	0	0
T39	0	29	0	0
T40	6438	2	0	0
T41	0	11	0	0
T48	0	1	0	0
T50	139500	0	0	0
T51	1151620	0	0	0
T55	0	2	0	0
T78	0	2	0	0
T104	0	1	0	0
T118	0	3	0	0
T173	0	26	0	0
T189	0	23	0	0
T195	0	2	0	0
T284	0	1	0	0
T285	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2060	2060	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T10	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T282
1	0	Covered	T7,T282

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T282

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T282
1	0	Covered	T1,T2,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T39

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T40,T41,T39

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T41,T39

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T49
1	0	Covered	T1,T4,T5
1	1	Covered	T40,T41,T39

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T41,T39

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T49,T40,T41
1	Covered	T1,T4,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T49
1	Covered	T1,T5,T49

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T49
1	Covered	T1,T5,T49

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T49
1	1	Covered	T1,T5,T49

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T29
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T49
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T5,T49

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T49

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T5,T42
StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc	215	Covered	T1,T4,T5
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T5
StPostPack	218	Covered	T40,T41,T39
StPrePack	195	Covered	T40,T41,T39
StReqFlash	237	Covered	T1,T5,T49
StScrambleData	244	Covered	T1,T5,T42
StWaitFlash	270	Covered	T1,T5,T49

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T5,T42
StCalcMask->StScrambleData	244	Covered	T1,T5,T42
StCalcPlainEcc->StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc->StReqFlash	237	Covered	T49,T40,T41
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T1,T4,T5
StIdle->StPrePack	195	Covered	T40,T41,T39
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T5
StPackData->StPostPack	218	Covered	T40,T41,T39
StPostPack->StCalcPlainEcc	231	Covered	T40,T41,T39
StPrePack->StPackData	205	Covered	T40,T41,T39
StReqFlash->StIdle	273	Covered	T1,T5,T49
StReqFlash->StWaitFlash	270	Covered	T1,T5,T49
StScrambleData->StCalcEcc	252	Covered	T1,T5,T42
StWaitFlash->StIdle	280	Covered	T1,T5,T49

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T49
0	1	Covered	T2,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T41,T39
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T41,T39
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T40,T41,T39
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T40,T41,T39
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T49,T40,T41
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T5,T42
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T5,T42
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T5,T49
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T5,T49
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T5,T49
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T5,T49
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T49
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T49
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T12,T13

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T5,T49
0	0	1	-	-	Covered	T1,T5,T42
0	0	0	1	-	Covered	T1,T5,T42
0	0	0	0	1	Covered	T1,T4,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T49
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	395334231	1208310	0	0
PostPackRule_A	395334231	1019	0	0
PrePackRule_A	395334231	672	0	0
WidthCheck_A	1030	1030	0	0
u_state_regs_A	395334231	394538632	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	1208310	0	0
T1	186735	576	0	0
T2	47732	0	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	449	0	0
T6	63225	0	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T21	0	32768	0	0
T40	0	4	0	0
T41	0	12	0	0
T42	0	682	0	0
T49	0	50	0	0
T50	0	148	0	0
T59	0	1	0	0
T60	0	169	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	1019	0	0
T11	3609	0	0	0
T17	153132	0	0	0
T18	858	0	0	0
T21	393427	0	0	0
T23	0	6	0	0
T25	128426	0	0	0
T28	72103	0	0	0
T29	74226	0	0	0
T39	0	20	0	0
T40	3219	3	0	0
T41	0	7	0	0
T50	69750	0	0	0
T51	575810	0	0	0
T55	0	1	0	0
T78	0	2	0	0
T173	0	19	0	0
T189	0	18	0	0
T283	0	1	0	0
T284	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	672	0	0
T11	3609	0	0	0
T17	153132	0	0	0
T18	858	0	0	0
T21	393427	0	0	0
T23	0	4	0	0
T25	128426	0	0	0
T28	72103	0	0	0
T29	74226	0	0	0
T39	0	12	0	0
T40	3219	1	0	0
T41	0	7	0	0
T50	69750	0	0	0
T51	575810	0	0	0
T55	0	2	0	0
T118	0	3	0	0
T173	0	14	0	0
T189	0	14	0	0
T284	0	1	0	0
T285	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T166,T281
1	0	Covered	T7,T166,T281

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T7,T166,T281

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T282
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T166,T281
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T40,T21,T104

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T40,T104,T41

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T104,T41

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T1,T5,T15

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T40,T104,T137

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8
1	Covered	T40,T104,T137

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T15,T49,T40
1	Covered	T1,T5,T42

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T1,T5,T15

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T1,T5,T15

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T42
1	1	Covered	T1,T5,T42

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T1,T5,T15
1	1	1	Covered	T1,T5,T15

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T5,T42
StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc	215	Covered	T1,T5,T15
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T5,T15
StPostPack	218	Covered	T40,T104,T137
StPrePack	195	Covered	T40,T104,T41
StReqFlash	237	Covered	T1,T5,T15
StScrambleData	244	Covered	T1,T5,T42
StWaitFlash	270	Covered	T1,T5,T15

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T5,T42
StCalcMask->StScrambleData	244	Covered	T1,T5,T42
StCalcPlainEcc->StCalcMask	237	Covered	T1,T5,T42
StCalcPlainEcc->StReqFlash	237	Covered	T15,T49,T40
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T1,T5,T15
StIdle->StPrePack	195	Covered	T40,T104,T41
StPackData->StCalcPlainEcc	215	Covered	T1,T5,T15
StPackData->StPostPack	218	Covered	T40,T104,T137
StPostPack->StCalcPlainEcc	231	Covered	T40,T104,T137
StPrePack->StPackData	205	Covered	T40,T104,T41
StReqFlash->StIdle	273	Covered	T1,T5,T15
StReqFlash->StWaitFlash	270	Covered	T1,T5,T15
StScrambleData->StCalcEcc	252	Covered	T1,T5,T42
StWaitFlash->StIdle	280	Covered	T1,T5,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T15
0	0	1	Covered	T1,T5,T15
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T41
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T41
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T40,T104,T137
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T5,T15
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T40,T104,T137
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T5,T42
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T15,T49,T40
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T5,T42
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T5,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T5,T42
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T5,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T5,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T15
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T12,T13

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T5,T15
0	0	1	-	-	Covered	T1,T5,T42
0	0	0	1	-	Covered	T1,T5,T42
0	0	0	0	1	Covered	T1,T5,T15
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	395334231	1231262	0	0
PostPackRule_A	395334231	980	0	0
PrePackRule_A	395334231	746	0	0
WidthCheck_A	1030	1030	0	0
u_state_regs_A	395334231	394538632	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	1231262	0	0
T1	186735	761	0	0
T2	47732	0	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	932	0	0
T6	63225	0	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	1	0	0
T16	4263	0	0	0
T17	0	184	0	0
T21	0	33152	0	0
T26	0	1	0	0
T40	0	2	0	0
T42	0	845	0	0
T49	0	50	0	0
T50	0	161	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	980	0	0
T11	3609	0	0	0
T17	153132	0	0	0
T18	858	0	0	0
T21	393427	0	0	0
T23	0	1	0	0
T25	128426	0	0	0
T28	72103	0	0	0
T29	74226	0	0	0
T39	0	31	0	0
T40	3219	2	0	0
T48	0	1	0	0
T50	69750	0	0	0
T51	575810	0	0	0
T78	0	3	0	0
T104	0	2	0	0
T137	0	1	0	0
T173	0	13	0	0
T189	0	13	0	0
T195	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	746	0	0
T11	3609	0	0	0
T17	153132	0	0	0
T18	858	0	0	0
T21	393427	0	0	0
T23	0	1	0	0
T25	128426	0	0	0
T28	72103	0	0	0
T29	74226	0	0	0
T39	0	17	0	0
T40	3219	1	0	0
T41	0	4	0	0
T48	0	1	0	0
T50	69750	0	0	0
T51	575810	0	0	0
T78	0	2	0	0
T104	0	1	0	0
T173	0	12	0	0
T189	0	9	0	0
T195	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0