Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27369923	1		T1	147		T2	935		T3	116
full_word	7849128	1		T1	59		T2	793		T3	45

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35218771	1		T1	206		T2	1728		T3	161
auto[TlIntgErrCmd]	78	1		T54	2		T55	3		T229	1
auto[TlIntgErrData]	97	1		T54	4		T55	5		T229	6
auto[TlIntgErrBoth]	105	1		T54	4		T55	2		T229	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30582694	1		T1	58		T2	1665		T3	115
auto[1]	4636357	1		T1	148		T2	63		T3	46

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26624705	1		T1	58		T2	928		T3	114
auto[TlIntgErrNone]	partial	auto[1]	744955	1		T1	89		T2	7		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	3957869	1		T2	737		T3	1		T4	89
auto[TlIntgErrNone]	full_word	auto[1]	3891242	1		T1	59		T2	56		T3	44
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T55	1		T256	1		T297	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T54	2		T55	2		T229	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T372	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T369	1		T373	1		T372	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T54	2		T55	4		T229	2
auto[TlIntgErrData]	partial	auto[1]	49	1		T54	2		T55	1		T229	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T229	1		T260	1		T296	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T290	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T54	1		T55	1		T229	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T54	3		T55	1		T229	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T297	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T260	2		T256	1		T295	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18165	1		T53	138		T54	8		T55	6
full_word	4121353	1		T4	245		T5	37120		T6	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4139259	1		T4	245		T5	37120		T6	10
auto[TlIntgErrCmd]	84	1		T54	5		T55	2		T229	2
auto[TlIntgErrData]	95	1		T54	5		T55	2		T229	2
auto[TlIntgErrBoth]	80	1		T55	4		T229	4		T260	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4115596	1		T4	245		T5	37120		T6	10
auto[1]	23922	1		T53	153		T54	7		T55	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	991	1		T53	5		T225	64		T226	5
auto[TlIntgErrNone]	partial	auto[1]	16946	1		T53	133		T225	1041		T226	104
auto[TlIntgErrNone]	full_word	auto[0]	4114504	1		T4	245		T5	37120		T6	10
auto[TlIntgErrNone]	full_word	auto[1]	6818	1		T53	20		T225	390		T226	10
auto[TlIntgErrCmd]	partial	auto[0]	19	1		T54	1		T55	2		T229	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T54	3		T229	1		T260	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T297	1		T374	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T54	1		T256	2		T297	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T54	1		T55	1		T229	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T54	3		T260	3		T297	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T54	1		T374	1		T372	2
auto[TlIntgErrData]	full_word	auto[1]	6	1		T55	1		T260	1		T297	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T55	1		T229	3		T295	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T55	2		T229	1		T260	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T371	1		T375	1		T372	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T55	1		T260	1		T297	1