Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.43	100.00	77.05			96.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo	83.75	100.00	64.66			85.71	84.62
tb.dut.u_to_rd_fifo	93.69	100.00	78.23			96.55	100.00
tb.dut.u_tl_adapter_eflash	96.21	100.00	88.28			96.55	100.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.75	100.00	64.66			85.71	84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.88	89.61	64.43			80.23	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	97.12	94.40	98.44		100.00	98.57	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	79.64	100.00	68.57			50.00	100.00
u_reqfifo	92.36	100.00	75.00			94.44	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	69.33	91.43	57.14			68.75	60.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	72.63	94.44	54.84			81.25	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.69	100.00	78.23			96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.87	87.80	76.06	80.00		85.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	97.12	94.40	98.44		100.00	98.57	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	89.38	100.00	76.92	80.00		90.00	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	90.08	100.00	78.72	80.00		91.67	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	88.87	100.00	74.36	80.00		90.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	100.00	88.28			96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.36	92.91	87.35	100.00		96.55	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	97.12	94.40	98.44		100.00	98.57	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
gen_data_xor_addr_fifo.u_sramreqaddrfifo	96.53	100.00	86.11			100.00	100.00
u_err	89.46	100.00	82.86			75.00	100.00
u_reqfifo	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	97.87	100.00	89.36	100.00		100.00	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	97.44	100.00	87.18	100.00		100.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
83.75	100.00

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		67	67	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	0	0
CONT_ASSIGN	479	0	0
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	0	0
ALWAYS	496	4	4	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
162	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477		unreachable
479		unreachable
481	1	1
490		unreachable
496	1	1
500	1	1
502	1	1
509		unreachable
511		unreachable
514	1	1
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
93.69	100.00

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	496	4	4	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
496	1	1
500	1	1
502	1	1
509		unreachable
511		unreachable
514	1	1
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
96.21	100.00

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		72	72	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	496	5	5	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
496	1	1
500	1	1
502	1	1
509	1	1
511	1	1
514		unreachable
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
83.75	64.66

tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	116	75	64.66
Logical	116	75	64.66
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T21
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T44,T8
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T4,T5,T6
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
93.69	78.23

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	124	97	78.23
Logical	124	97	78.23
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T25
0	0	1	0	Covered	T18,T25
0	1	0	0	Covered	T18,T25
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T18,T25
0	0	0	1	0	Covered	T18,T25
0	0	1	0	0	Covered	T18,T25
0	1	0	0	0	Covered	T18,T25
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T27,T7
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15
1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15
1	Covered	T4,T5,T6

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T56,T57,T58

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T57,T58
1	1	Covered	T4,T5,T6

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T56,T57,T58

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T27,T21,T49
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T21,T49
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
96.21	88.28

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	128	113	88.28
Logical	128	113	88.28
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T25
0	0	1	0	Covered	T18,T25
0	1	0	0	Covered	T18,T25
1	0	0	0	Covered	T23,T59,T60

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T18,T23,T59
0	0	0	1	0	Covered	T18,T25
0	0	1	0	0	Covered	T18,T25
0	1	0	0	0	Covered	T18,T25
1	0	0	0	0	Covered	T23,T59,T60

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T5,T8,T22
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T22

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T33
0	1	Covered	T5,T8,T22
1	0	Covered	T3,T5,T8

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T5,T8,T22
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T2,T3,T5
0	0	0	1	0	0	Covered	T51,T46,T61
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T61,T62,T63
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T22
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T63
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16
1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T23
1	Covered	T4,T5,T6

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T51,T46,T61
1	0	Covered	T5,T7,T40

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T51,T46,T61
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T40
1	1	Covered	T4,T5,T6

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T51,T46,T61
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T51,T46,T61
1	1	1	Covered	T51,T46,T61

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T59

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T23,T59

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T7,T40

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T46,T47,T50
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T46,T61
1	0	Covered	T4,T5,T6

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T51,T46,T61
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T59

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T59

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T59

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T46,T61
1	1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		30	29	96.67
TERNARY	144	2	2	100.00
TERNARY	343	2	2	100.00
TERNARY	349	3	2	66.67
TERNARY	395	2	2	100.00
TERNARY	535	2	2	100.00
IF	129	3	3	100.00
IF	283	4	4	100.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00
IF	500	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T51,T46,T61
1	0	1	Covered	T4,T5,T6
1	0	0	Covered	T4,T5,T6
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	500	if ((|sramreqfifo_rdata.mask))
-2-:	502	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1133419638	1130812665	0	0
DataIntgOptions_A	3084	3084	0	0
ReqOutKnown_A	1133419638	1130812665	0	0
SramDwHasByteGranularity_A	3084	3084	0	0
SramDwIsMultipleOfTlulWidth_A	3084	3084	0	0
TlOutKnownIfFifoKnown_A	1133419638	1130812665	0	0
TlOutValidKnown_A	1133419638	1130812665	0	0
WdataOutKnown_A	1133419638	1130812665	0	0
WeOutKnown_A	1133419638	1130812665	0	0
WmaskOutKnown_A	1133419638	1130812665	0	0
adapterNoReadOrWrite	3084	3084	0	0
rvalidHighReqFifoEmpty	1133419638	7462354	0	0
rvalidHighWhenRspFifoFull	1132930058	7458800	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3084	3084	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3084	3084	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3084	3084	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	1130812665	0	0
T1	11589	11379	0	0
T2	1212624	1212576	0	0
T3	2681844	2681517	0	0
T4	418035	417864	0	0
T5	1068855	1068564	0	0
T6	7101	6708	0	0
T13	11274	9072	0	0
T14	2220	2052	0	0
T19	11109	8952	0	0
T20	6183	5946	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	3084	3084	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133419638	7462354	0	0
T4	278690	322	0	0
T5	712570	47245	0	0
T6	4734	88	0	0
T7	3154	41	0	0
T8	0	311	0	0
T9	0	388	0	0
T13	7516	0	0	0
T14	1480	10	0	0
T19	7406	0	0	0
T20	4122	0	0	0
T22	0	999	0	0
T26	0	16	0	0
T27	4030	14	0	0
T44	8838	7	0	0
T48	0	121	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132930058	7458800	0	0
T4	278690	322	0	0
T5	712570	47245	0	0
T6	4734	88	0	0
T7	3154	41	0	0
T8	0	311	0	0
T9	0	388	0	0
T13	7516	0	0	0
T14	1480	10	0	0
T19	7406	0	0	0
T20	4122	0	0	0
T22	0	999	0	0
T26	0	16	0	0
T27	4030	14	0	0
T44	8838	7	0	0
T48	0	121	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		67	67	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	0	0
CONT_ASSIGN	479	0	0
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	0	0
ALWAYS	496	4	4	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
162	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477		unreachable
479		unreachable
481	1	1
490		unreachable
496	1	1
500	1	1
502	1	1
509		unreachable
511		unreachable
514	1	1
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	116	75	64.66
Logical	116	75	64.66
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T21
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T44,T8
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T4,T5,T6
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		28	24	85.71
TERNARY	144	2	2	100.00
TERNARY	343	2	1	50.00
TERNARY	349	3	1	33.33
TERNARY	395	2	2	100.00
TERNARY	535	2	1	50.00
IF	129	2	2	100.00
IF	283	4	4	100.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00
IF	500	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T15,T16
1	0	1	Covered	T15,T16
1	0	0	Covered	T4,T5,T6
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T15,T16
1	0	Covered	T4,T5,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	500	if ((|sramreqfifo_rdata.mask))
-2-:	502	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Unreachable
1	0	Covered	T15,T16
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	377806546	376937555	0	0
DataIntgOptions_A	1028	1028	0	0
ReqOutKnown_A	377806546	376937555	0	0
SramDwHasByteGranularity_A	1028	1028	0	0
SramDwIsMultipleOfTlulWidth_A	1028	1028	0	0
TlOutKnownIfFifoKnown_A	377806546	376937555	0	0
TlOutValidKnown_A	377806546	376937555	0	0
WdataOutKnown_A	377806546	376937555	0	0
WeOutKnown_A	377806546	376937555	0	0
WmaskOutKnown_A	377806546	376937555	0	0
adapterNoReadOrWrite	1028	1028	0	0
rvalidHighReqFifoEmpty	377806546	0	0	0
rvalidHighWhenRspFifoFull	377806546	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	496	4	4	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
496	1	1
500	1	1
502	1	1
509		unreachable
511		unreachable
514	1	1
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	124	97	78.23
Logical	124	97	78.23
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T25
0	0	1	0	Covered	T18,T25
0	1	0	0	Covered	T18,T25
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T18,T25
0	0	0	1	0	Covered	T18,T25
0	0	1	0	0	Covered	T18,T25
0	1	0	0	0	Covered	T18,T25
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T27,T7
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15
1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15
1	Covered	T4,T5,T6

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T56,T57,T58

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T57,T58
1	1	Covered	T4,T5,T6

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T56,T57,T58

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T27,T21,T49
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T21,T49
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	144	2	2	100.00
TERNARY	343	2	2	100.00
TERNARY	349	3	2	66.67
TERNARY	395	2	2	100.00
TERNARY	535	2	2	100.00
IF	129	3	3	100.00
IF	283	4	4	100.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00
IF	500	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T15,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T15
1	0	1	Covered	T4,T5,T6
1	0	0	Covered	T15
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T15
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	500	if ((|sramreqfifo_rdata.mask))
-2-:	502	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Unreachable
1	0	Covered	T4,T5,T6
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	377806546	376937555	0	0
DataIntgOptions_A	1028	1028	0	0
ReqOutKnown_A	377806546	376937555	0	0
SramDwHasByteGranularity_A	1028	1028	0	0
SramDwIsMultipleOfTlulWidth_A	1028	1028	0	0
TlOutKnownIfFifoKnown_A	377806546	376937555	0	0
TlOutValidKnown_A	377806546	376937555	0	0
WdataOutKnown_A	377806546	376937555	0	0
WeOutKnown_A	377806546	376937555	0	0
WmaskOutKnown_A	377806546	376937555	0	0
adapterNoReadOrWrite	1028	1028	0	0
rvalidHighReqFifoEmpty	377806546	3244333	0	0
rvalidHighWhenRspFifoFull	377316966	3240779	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	3244333	0	0
T4	139345	77	0	0
T5	356285	6125	0	0
T6	2367	78	0	0
T7	1577	32	0	0
T8	0	76	0	0
T9	0	253	0	0
T13	3758	0	0	0
T14	740	0	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	927	0	0
T27	2015	14	0	0
T44	4419	7	0	0
T48	0	23	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	377316966	3240779	0	0
T4	139345	77	0	0
T5	356285	6125	0	0
T6	2367	78	0	0
T7	1577	32	0	0
T8	0	76	0	0
T9	0	253	0	0
T13	3758	0	0	0
T14	740	0	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	927	0	0
T27	2015	14	0	0
T44	4419	7	0	0
T48	0	23	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		72	72	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	8	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	496	5	5	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	1	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
448	1	1
449	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
496	1	1
500	1	1
502	1	1
509	1	1
511	1	1
514		unreachable
			MISSING_ELSE
530	1	1
535	1	1
540		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	128	113	88.28
Logical	128	113	88.28
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T25
0	0	1	0	Covered	T18,T25
0	1	0	0	Covered	T18,T25
1	0	0	0	Covered	T23,T59,T60

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T18,T23,T59
0	0	0	1	0	Covered	T18,T25
0	0	1	0	0	Covered	T18,T25
0	1	0	0	0	Covered	T18,T25
1	0	0	0	0	Covered	T23,T59,T60

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T5,T8,T22
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T22

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T33
0	1	Covered	T5,T8,T22
1	0	Covered	T3,T5,T8

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T5,T8,T22
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T2,T3,T5
0	0	0	1	0	0	Covered	T51,T46,T61
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T61,T62,T63
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T22
1	1	Covered	T4,T5,T6

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T63
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16
1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T23
1	Covered	T4,T5,T6

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T51,T46,T61
1	0	Covered	T5,T7,T40

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T51,T46,T61
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T40
1	1	Covered	T4,T5,T6

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T51,T46,T61
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T51,T46,T61
1	1	1	Covered	T51,T46,T61

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T59

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T23,T59

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T7,T40

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T46,T47,T50
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T5,T6

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T46,T61
1	0	Covered	T4,T5,T6

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T51,T46,T61
1	1	1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T59

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T59

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T59

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T46,T61
1	1	Covered	T4,T5,T6

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	144	2	2	100.00
TERNARY	343	2	2	100.00
TERNARY	349	3	2	66.67
TERNARY	395	2	2	100.00
TERNARY	535	2	2	100.00
IF	129	3	3	100.00
IF	283	4	4	100.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00
IF	500	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T51,T46,T61
1	0	1	Covered	T4,T5,T6
1	0	0	Covered	T15,T16
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T15,T16,T23
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	500	if ((|sramreqfifo_rdata.mask))
-2-:	502	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Unreachable
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	377806546	376937555	0	0
DataIntgOptions_A	1028	1028	0	0
ReqOutKnown_A	377806546	376937555	0	0
SramDwHasByteGranularity_A	1028	1028	0	0
SramDwIsMultipleOfTlulWidth_A	1028	1028	0	0
TlOutKnownIfFifoKnown_A	377806546	376937555	0	0
TlOutValidKnown_A	377806546	376937555	0	0
WdataOutKnown_A	377806546	376937555	0	0
WeOutKnown_A	377806546	376937555	0	0
WmaskOutKnown_A	377806546	376937555	0	0
adapterNoReadOrWrite	1028	1028	0	0
rvalidHighReqFifoEmpty	377806546	4218021	0	0
rvalidHighWhenRspFifoFull	377806546	4218021	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	4218021	0	0
T4	139345	245	0	0
T5	356285	41120	0	0
T6	2367	10	0	0
T7	1577	9	0	0
T8	0	235	0	0
T9	0	135	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	72	0	0
T26	0	16	0	0
T27	2015	0	0	0
T44	4419	0	0	0
T48	0	98	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	4218021	0	0
T4	139345	245	0	0
T5	356285	41120	0	0
T6	2367	10	0	0
T7	1577	9	0	0
T8	0	235	0	0
T9	0	135	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	72	0	0
T26	0	16	0	0
T27	2015	0	0	0
T44	4419	0	0	0
T48	0	98	0	0