Unified Coverage Report :: Module :: prim_secded_inv_39_32_enc

Module : prim_secded_inv_39_32_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen	0.00	0.00
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen	0.00	0.00
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen	0.00	0.00
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen	0.00	0.00
tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen	0.00	0.00
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen	0.00	0.00
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen	0.00	0.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen	100.00	100.00
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen	100.00	100.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_instr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_instr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_instr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_bus_inv_data_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_bus_inv_data_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rd.gen_bus_words_intg[0].u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rd.gen_bus_words_intg[1].u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rd.gen_bus_words_intg[0].u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rd.gen_bus_words_intg[1].u_bus_intg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_secded_inv_39_32_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
ALWAYS	13	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	0	1
14	0	1
15	0	1
16	0	1
17	0	1
18	0	1
19	0	1
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1