Module Definition
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Module : prim_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_ctrl_arb.u_state_regs.u_state_flop
tb.dut.u_flash_hw_if.u_state_regs.u_state_flop
tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_flash_hw_if.u_rma_state_regs.u_state_flop
tb.dut.u_flash_hw_if.u_prim_flop_err_sts
tb.dut.u_prog_tl_gate.u_state_regs.u_state_flop
tb.dut.u_reg_idle
tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_tl_gate.u_state_regs.u_state_flop
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.u_state_flop
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.u_state_flop
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.u_state_flop
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.u_state_flop



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_ctrl_arb.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_rma_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_rma_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_prim_flop_err_sts

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.96 100.00 93.75 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_idle

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 97.12 94.40 98.44 100.00 98.57 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00

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