Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1511226184	1507750220	0	0
CheckNGreaterZero_A	4112	4112	0	0
GntImpliesReady_A	1511226184	415650968	0	0
GntImpliesValid_A	1511226184	415650968	0	0
GrantKnown_A	1511226184	1507750220	0	0
IdxKnown_A	1511226184	1507750220	0	0
IndexIsCorrect_A	1511226184	415650968	0	0
NoReadyValidNoGrant_A	1511226184	173214735	0	0
Priority_A	1511226184	439652093	0	0
ReadyAndValidImplyGrant_A	1511226184	415650968	0	0
ReqAndReadyImplyGrant_A	1511226184	415650968	0	0
ReqImpliesValid_A	1511226184	439652093	0	0
ValidKnown_A	1511226184	1507750220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	1507750220	0	0
T1	15452	15172	0	0
T2	1616832	1616768	0	0
T3	3575792	3575356	0	0
T4	557380	557152	0	0
T5	1425140	1424752	0	0
T6	9468	8944	0	0
T13	15032	12096	0	0
T14	2960	2736	0	0
T19	14812	11936	0	0
T20	8244	7928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4112	4112	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	415650968	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269676	0	0
T5	1425140	430530	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3468	0	0
T9	0	256	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20070	0	0
T27	4030	0	0	0
T44	0	1266	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	415650968	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269676	0	0
T5	1425140	430530	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3468	0	0
T9	0	256	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20070	0	0
T27	4030	0	0	0
T44	0	1266	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	1507750220	0	0
T1	15452	15172	0	0
T2	1616832	1616768	0	0
T3	3575792	3575356	0	0
T4	557380	557152	0	0
T5	1425140	1424752	0	0
T6	9468	8944	0	0
T13	15032	12096	0	0
T14	2960	2736	0	0
T19	14812	11936	0	0
T20	8244	7928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	1507750220	0	0
T1	15452	15172	0	0
T2	1616832	1616768	0	0
T3	3575792	3575356	0	0
T4	557380	557152	0	0
T5	1425140	1424752	0	0
T6	9468	8944	0	0
T13	15032	12096	0	0
T14	2960	2736	0	0
T19	14812	11936	0	0
T20	8244	7928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	415650968	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269676	0	0
T5	1425140	430530	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3468	0	0
T9	0	256	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20070	0	0
T27	4030	0	0	0
T44	0	1266	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	173214735	0	0
T1	7726	256	0	0
T2	1616832	2109952	0	0
T3	3575792	352	0	0
T4	557380	1996	0	0
T5	1425140	329980	0	0
T6	9468	950	0	0
T7	0	42	0	0
T8	0	640	0	0
T9	0	150	0	0
T13	15032	1148	0	0
T14	2960	288	0	0
T19	14812	1628	0	0
T20	8244	256	0	0
T22	0	1828	0	0
T27	4030	0	0	0
T48	0	134	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	439652093	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269824	0	0
T5	1425140	495050	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3562	0	0
T9	0	336	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20086	0	0
T27	4030	0	0	0
T44	0	1266	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	415650968	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269676	0	0
T5	1425140	430530	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3468	0	0
T9	0	256	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20070	0	0
T27	4030	0	0	0
T44	0	1266	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	415650968	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269676	0	0
T5	1425140	430530	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3468	0	0
T9	0	256	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20070	0	0
T27	4030	0	0	0
T44	0	1266	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	439652093	0	0
T1	7726	64	0	0
T2	1616832	514598	0	0
T3	3575792	1378	0	0
T4	557380	269824	0	0
T5	1425140	495050	0	0
T6	9468	770	0	0
T7	0	18	0	0
T8	0	3562	0	0
T9	0	336	0	0
T13	15032	326	0	0
T14	2960	84	0	0
T19	14812	434	0	0
T20	8244	64	0	0
T22	0	20086	0	0
T27	4030	0	0	0
T44	0	1266	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1511226184	1507750220	0	0
T1	15452	15172	0	0
T2	1616832	1616768	0	0
T3	3575792	3575356	0	0
T4	557380	557152	0	0
T5	1425140	1424752	0	0
T6	9468	8944	0	0
T13	15032	12096	0	0
T14	2960	2736	0	0
T19	14812	11936	0	0
T20	8244	7928	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377806546	376937555	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	377806546	110425884	0	0
GntImpliesValid_A	377806546	110425884	0	0
GrantKnown_A	377806546	376937555	0	0
IdxKnown_A	377806546	376937555	0	0
IndexIsCorrect_A	377806546	110425884	0	0
NoReadyValidNoGrant_A	377806546	44966867	0	0
Priority_A	377806546	116477199	0	0
ReadyAndValidImplyGrant_A	377806546	110425884	0	0
ReqAndReadyImplyGrant_A	377806546	110425884	0	0
ReqImpliesValid_A	377806546	116477199	0	0
ValidKnown_A	377806546	376937555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425884	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425884	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425884	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	44966867	0	0
T1	3863	128	0	0
T2	404208	530688	0	0
T3	893948	176	0	0
T4	139345	831	0	0
T5	356285	89727	0	0
T6	2367	435	0	0
T13	3758	574	0	0
T14	740	128	0	0
T19	3703	814	0	0
T20	2061	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	116477199	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134213	0	0
T5	356285	125276	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425884	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425884	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	116477199	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134213	0	0
T5	356285	125276	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377806546	376937555	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	377806546	110425890	0	0
GntImpliesValid_A	377806546	110425890	0	0
GrantKnown_A	377806546	376937555	0	0
IdxKnown_A	377806546	376937555	0	0
IndexIsCorrect_A	377806546	110425890	0	0
NoReadyValidNoGrant_A	377806546	44966812	0	0
Priority_A	377806546	116477260	0	0
ReadyAndValidImplyGrant_A	377806546	110425890	0	0
ReqAndReadyImplyGrant_A	377806546	110425890	0	0
ReqImpliesValid_A	377806546	116477260	0	0
ValidKnown_A	377806546	376937555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425890	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425890	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425890	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	44966812	0	0
T1	3863	128	0	0
T2	404208	530688	0	0
T3	893948	176	0	0
T4	139345	831	0	0
T5	356285	89727	0	0
T6	2367	435	0	0
T13	3758	574	0	0
T14	740	128	0	0
T19	3703	814	0	0
T20	2061	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	116477260	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134213	0	0
T5	356285	125276	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425890	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	110425890	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134139	0	0
T5	356285	103153	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	116477260	0	0
T1	3863	32	0	0
T2	404208	129402	0	0
T3	893948	689	0	0
T4	139345	134213	0	0
T5	356285	125276	0	0
T6	2367	369	0	0
T13	3758	163	0	0
T14	740	32	0	0
T19	3703	217	0	0
T20	2061	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T14
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T9
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377806546	376937555	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	377806546	97399597	0	0
GntImpliesValid_A	377806546	97399597	0	0
GrantKnown_A	377806546	376937555	0	0
IdxKnown_A	377806546	376937555	0	0
IndexIsCorrect_A	377806546	97399597	0	0
NoReadyValidNoGrant_A	377806546	41640528	0	0
Priority_A	377806546	103348817	0	0
ReadyAndValidImplyGrant_A	377806546	97399597	0	0
ReqAndReadyImplyGrant_A	377806546	97399597	0	0
ReqImpliesValid_A	377806546	103348817	0	0
ValidKnown_A	377806546	376937555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	41640528	0	0
T2	404208	524288	0	0
T3	893948	0	0	0
T4	139345	167	0	0
T5	356285	75263	0	0
T6	2367	40	0	0
T7	0	21	0	0
T8	0	320	0	0
T9	0	75	0	0
T13	3758	0	0	0
T14	740	16	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	914	0	0
T27	2015	0	0	0
T48	0	67	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	103348817	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	122249	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1781	0	0
T9	0	168	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10043	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	103348817	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	122249	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1781	0	0
T9	0	168	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10043	0	0
T27	2015	0	0	0
T44	0	633	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T14
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T9
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377806546	376937555	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	377806546	97399597	0	0
GntImpliesValid_A	377806546	97399597	0	0
GrantKnown_A	377806546	376937555	0	0
IdxKnown_A	377806546	376937555	0	0
IndexIsCorrect_A	377806546	97399597	0	0
NoReadyValidNoGrant_A	377806546	41640528	0	0
Priority_A	377806546	103348817	0	0
ReadyAndValidImplyGrant_A	377806546	97399597	0	0
ReqAndReadyImplyGrant_A	377806546	97399597	0	0
ReqImpliesValid_A	377806546	103348817	0	0
ValidKnown_A	377806546	376937555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	41640528	0	0
T2	404208	524288	0	0
T3	893948	0	0	0
T4	139345	167	0	0
T5	356285	75263	0	0
T6	2367	40	0	0
T7	0	21	0	0
T8	0	320	0	0
T9	0	75	0	0
T13	3758	0	0	0
T14	740	16	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	914	0	0
T27	2015	0	0	0
T48	0	67	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	103348817	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	122249	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1781	0	0
T9	0	168	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10043	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	97399597	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	112112	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1734	0	0
T9	0	128	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10035	0	0
T27	2015	0	0	0
T44	0	633	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	103348817	0	0
T2	404208	127897	0	0
T3	893948	0	0	0
T4	139345	699	0	0
T5	356285	122249	0	0
T6	2367	16	0	0
T7	0	9	0	0
T8	0	1781	0	0
T9	0	168	0	0
T13	3758	0	0	0
T14	740	10	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	10043	0	0
T27	2015	0	0	0
T44	0	633	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0