Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	100.00	90.81			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.48	100.00	89.93			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.59	100.00	90.37			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.48	100.00	89.93			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.13	97.64	92.74	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.59	100.00	90.37			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.17	97.64	92.90	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	457	415	90.81
Logical	457	415	90.81
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
141-792	91.05
792-796	80.00

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T24,T186
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T14,T27

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	755613092	1611354	0	0
ExclusiveOps_A	755613092	753875110	0	0
ExclusiveProgHazard_A	755613092	753875110	0	0
ExclusiveState_A	755613092	753875110	0	0
ForwardCheck_A	755613092	3944728	0	0
IdleCheck_A	755613092	99899245	0	0
MaxBufs_A	2056	2056	0	0
OneHotAlloc_A	755613092	753875110	0	0
OneHotMatch_A	755613092	753875110	0	0
OneHotRspMatch_A	755613092	753875110	0	0
OneHotUpdate_A	755613092	753875110	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	1611354	0	0
T4	278690	147	0	0
T5	712570	1769	0	0
T6	4734	35	0	0
T7	3154	16	0	0
T8	0	143	0	0
T9	0	153	0	0
T13	7516	0	0	0
T14	1480	4	0	0
T19	7406	0	0	0
T20	4122	0	0	0
T21	0	188	0	0
T22	0	341	0	0
T27	4030	5	0	0
T44	8838	3	0	0
T48	0	59	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	3944728	0	0
T4	278690	175	0	0
T5	712570	0	0	0
T6	4734	0	0	0
T7	3154	3	0	0
T8	0	168	0	0
T9	0	235	0	0
T13	7516	0	0	0
T14	1480	6	0	0
T19	7406	0	0	0
T20	4122	0	0	0
T21	0	459	0	0
T26	0	20	0	0
T27	4030	9	0	0
T44	8838	4	0	0
T48	0	62	0	0
T49	0	139	0	0
T98	0	10	0	0
T121	0	79	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	99899245	0	0
T1	3863	128	0	0
T2	808416	1054976	0	0
T3	1787896	176	0	0
T4	278690	1026	0	0
T5	712570	216592	0	0
T6	4734	475	0	0
T7	0	21	0	0
T8	0	320	0	0
T9	0	111	0	0
T13	7516	574	0	0
T14	1480	144	0	0
T19	7406	814	0	0
T20	4122	128	0	0
T22	0	956	0	0
T27	2015	0	0	0
T48	0	67	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2056	2056	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T13	2	2	0	0
T14	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755613092	753875110	0	0
T1	7726	7586	0	0
T2	808416	808384	0	0
T3	1787896	1787678	0	0
T4	278690	278576	0	0
T5	712570	712376	0	0
T6	4734	4472	0	0
T13	7516	6048	0	0
T14	1480	1368	0	0
T19	7406	5968	0	0
T20	4122	3964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	457	411	89.93
Logical	457	411	89.93
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
141-792	90.02
792-796	83.33

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T22,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T6
0	1	Covered	T9,T24,T186
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T2,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T14,T7

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T2,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T40,T175
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	377806546	774953	0	0
ExclusiveOps_A	377806546	376937555	0	0
ExclusiveProgHazard_A	377806546	376937555	0	0
ExclusiveState_A	377806546	376937555	0	0
ForwardCheck_A	377806546	1851443	0	0
IdleCheck_A	377806546	48234602	0	0
MaxBufs_A	1028	1028	0	0
OneHotAlloc_A	377806546	376937555	0	0
OneHotMatch_A	377806546	376937555	0	0
OneHotRspMatch_A	377806546	376937555	0	0
OneHotUpdate_A	377806546	376937555	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	774953	0	0
T4	139345	49	0	0
T5	356285	778	0	0
T6	2367	8	0	0
T7	1577	3	0	0
T8	0	65	0	0
T9	0	13	0	0
T13	3758	0	0	0
T14	740	4	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T21	0	188	0	0
T22	0	189	0	0
T27	2015	0	0	0
T44	4419	0	0	0
T48	0	21	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	1851443	0	0
T4	139345	59	0	0
T5	356285	0	0	0
T6	2367	0	0	0
T7	1577	3	0	0
T8	0	77	0	0
T9	0	49	0	0
T13	3758	0	0	0
T14	740	6	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T21	0	217	0	0
T26	0	9	0	0
T27	2015	0	0	0
T44	4419	0	0	0
T48	0	23	0	0
T49	0	83	0	0
T98	0	10	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	48234602	0	0
T2	404208	524288	0	0
T3	893948	0	0	0
T4	139345	167	0	0
T5	356285	94955	0	0
T6	2367	40	0	0
T7	0	21	0	0
T8	0	320	0	0
T9	0	111	0	0
T13	3758	0	0	0
T14	740	16	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	956	0	0
T27	2015	0	0	0
T48	0	67	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	457	413	90.37
Logical	457	413	90.37
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
141-792	90.60
792-796	80.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T24,T186
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T27,T44
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T27,T44
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T27,T44

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T27,T44
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	377806546	836401	0	0
ExclusiveOps_A	377806546	376937555	0	0
ExclusiveProgHazard_A	377806546	376937555	0	0
ExclusiveState_A	377806546	376937555	0	0
ForwardCheck_A	377806546	2093285	0	0
IdleCheck_A	377806546	51664643	0	0
MaxBufs_A	1028	1028	0	0
OneHotAlloc_A	377806546	376937555	0	0
OneHotMatch_A	377806546	376937555	0	0
OneHotRspMatch_A	377806546	376937555	0	0
OneHotUpdate_A	377806546	376937555	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	836401	0	0
T4	139345	98	0	0
T5	356285	991	0	0
T6	2367	27	0	0
T7	1577	13	0	0
T8	0	78	0	0
T9	0	140	0	0
T13	3758	0	0	0
T14	740	0	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T22	0	152	0	0
T27	2015	5	0	0
T44	4419	3	0	0
T48	0	38	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	2093285	0	0
T4	139345	116	0	0
T5	356285	0	0	0
T6	2367	0	0	0
T7	1577	0	0	0
T8	0	91	0	0
T9	0	186	0	0
T13	3758	0	0	0
T14	740	0	0	0
T19	3703	0	0	0
T20	2061	0	0	0
T21	0	242	0	0
T26	0	11	0	0
T27	2015	9	0	0
T44	4419	4	0	0
T48	0	39	0	0
T49	0	56	0	0
T121	0	79	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	51664643	0	0
T1	3863	128	0	0
T2	404208	530688	0	0
T3	893948	176	0	0
T4	139345	859	0	0
T5	356285	121637	0	0
T6	2367	435	0	0
T13	3758	574	0	0
T14	740	128	0	0
T19	3703	814	0	0
T20	2061	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377806546	376937555	0	0
T1	3863	3793	0	0
T2	404208	404192	0	0
T3	893948	893839	0	0
T4	139345	139288	0	0
T5	356285	356188	0	0
T6	2367	2236	0	0
T13	3758	3024	0	0
T14	740	684	0	0
T19	3703	2984	0	0
T20	2061	1982	0	0