Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26885181	1		T1	145		T2	29378		T3	144
full_word	7873889	1		T1	50		T2	2781		T3	65

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34758760	1		T1	195		T2	32159		T3	209
auto[TlIntgErrCmd]	106	1		T76	5		T228	4		T254	3
auto[TlIntgErrData]	94	1		T76	5		T228	6		T254	5
auto[TlIntgErrBoth]	110	1		T76	10		T228	10		T254	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30231124	1		T1	140		T2	30133		T3	58
auto[1]	4527946	1		T1	55		T2	2026		T3	151

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26173395	1		T1	137		T2	29109		T3	57
auto[TlIntgErrNone]	partial	auto[1]	711501	1		T1	8		T2	269		T3	87
auto[TlIntgErrNone]	full_word	auto[0]	4057597	1		T1	3		T2	1024		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3816267	1		T1	47		T2	1757		T3	64
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T76	2		T228	1		T254	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T76	3		T228	3		T254	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T376	1		T383	1		T384	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T294	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1		T76	3		T228	1		T254	4
auto[TlIntgErrData]	partial	auto[1]	46	1		T76	2		T228	3		T254	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T228	1		T375	1		T381	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T228	1		T376	1		T294	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T76	4		T228	5		T253	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T76	6		T228	5		T254	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T376	1		T294	1		T385	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T382	1		T379	1		T386	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19841	1		T227	876		T75	441		T76	19
full_word	4205186	1		T4	16860		T13	18		T14	32

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4224732	1		T4	16860		T13	18		T14	32
auto[TlIntgErrCmd]	99	1		T76	4		T228	5		T254	4
auto[TlIntgErrData]	107	1		T76	5		T228	12		T254	4
auto[TlIntgErrBoth]	89	1		T76	10		T228	2		T254	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4199437	1		T4	16860		T13	18		T14	32
auto[1]	25590	1		T227	1236		T75	543		T76	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1138	1		T227	82		T75	29		T235	49
auto[TlIntgErrNone]	partial	auto[1]	18430	1		T227	794		T75	412		T235	617
auto[TlIntgErrNone]	full_word	auto[0]	4198154	1		T4	16860		T13	18		T14	32
auto[TlIntgErrNone]	full_word	auto[1]	7010	1		T227	442		T75	131		T235	315
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T76	3		T228	2		T254	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T76	1		T228	2		T254	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T294	1		T378	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T228	1		T383	1		-	-
auto[TlIntgErrData]	partial	auto[0]	56	1		T76	4		T228	3		T254	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T76	1		T228	8		T254	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T228	1		T377	1		T386	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T382	1		T387	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T76	5		T228	1		T254	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T76	5		T228	1		T254	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T253	1		T294	1		T383	3
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T374	1		T382	1		T388	1