Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T14

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1540101104	1536890008	0	0
CheckNGreaterZero_A	4144	4144	0	0
GntImpliesReady_A	1540101104	403419831	0	0
GntImpliesValid_A	1540101104	403419831	0	0
GrantKnown_A	1540101104	1536890008	0	0
IdxKnown_A	1540101104	1536890008	0	0
IndexIsCorrect_A	1540101104	403419831	0	0
NoReadyValidNoGrant_A	1540101104	178036062	0	0
Priority_A	1540101104	427855985	0	0
ReadyAndValidImplyGrant_A	1540101104	403419831	0	0
ReqAndReadyImplyGrant_A	1540101104	403419831	0	0
ReqImpliesValid_A	1540101104	427855985	0	0
ValidKnown_A	1540101104	1536890008	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	1536890008	0	0
T1	6232	5880	0	0
T2	1354884	1354520	0	0
T3	12540	12252	0	0
T4	601728	601188	0	0
T5	458488	437128	0	0
T12	4248	3352	0	0
T13	2436	2192	0	0
T17	14544	11608	0	0
T18	10744	10468	0	0
T19	12336	12040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4144	4144	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	403419831	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	83864	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	20170	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	403419831	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	83864	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	20170	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	1536890008	0	0
T1	6232	5880	0	0
T2	1354884	1354520	0	0
T3	12540	12252	0	0
T4	601728	601188	0	0
T5	458488	437128	0	0
T12	4248	3352	0	0
T13	2436	2192	0	0
T17	14544	11608	0	0
T18	10744	10468	0	0
T19	12336	12040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	1536890008	0	0
T1	6232	5880	0	0
T2	1354884	1354520	0	0
T3	12540	12252	0	0
T4	601728	601188	0	0
T5	458488	437128	0	0
T12	4248	3352	0	0
T13	2436	2192	0	0
T17	14544	11608	0	0
T18	10744	10468	0	0
T19	12336	12040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	403419831	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	83864	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	20170	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	178036062	0	0
T1	3116	256	0	0
T2	1354884	2886	0	0
T3	12540	256	0	0
T4	601728	230572	0	0
T5	458488	26048	0	0
T6	0	1334	0	0
T7	0	24934	0	0
T12	4248	536	0	0
T13	2436	352	0	0
T14	1420	166	0	0
T17	14544	1024	0	0
T18	10744	322	0	0
T19	12336	256	0	0
T29	0	80	0	0
T31	0	96	0	0
T32	0	348	0	0
T37	0	51212	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	427855985	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	87564	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	34410	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	403419831	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	83864	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	20170	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	403419831	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	83864	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	20170	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	427855985	0	0
T1	6232	402	0	0
T2	1354884	564368	0	0
T3	12540	64	0	0
T4	601728	87564	0	0
T5	458488	97670	0	0
T6	0	290312	0	0
T7	0	34410	0	0
T12	4248	134	0	0
T13	2436	100	0	0
T14	0	64	0	0
T17	14544	292	0	0
T18	10744	626	0	0
T19	12336	64	0	0
T29	0	20	0	0
T31	0	36	0	0
T32	0	144	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540101104	1536890008	0	0
T1	6232	5880	0	0
T2	1354884	1354520	0	0
T3	12540	12252	0	0
T4	601728	601188	0	0
T5	458488	437128	0	0
T12	4248	3352	0	0
T13	2436	2192	0	0
T17	14544	11608	0	0
T18	10744	10468	0	0
T19	12336	12040	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T29
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T29
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T29

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T29

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T29

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385025276	384222502	0	0
CheckNGreaterZero_A	1036	1036	0	0
GntImpliesReady_A	385025276	110829817	0	0
GntImpliesValid_A	385025276	110829817	0	0
GrantKnown_A	385025276	384222502	0	0
IdxKnown_A	385025276	384222502	0	0
IndexIsCorrect_A	385025276	110829817	0	0
NoReadyValidNoGrant_A	385025276	46644084	0	0
Priority_A	385025276	117039614	0	0
ReadyAndValidImplyGrant_A	385025276	110829817	0	0
ReqAndReadyImplyGrant_A	385025276	110829817	0	0
ReqImpliesValid_A	385025276	117039614	0	0
ValidKnown_A	385025276	384222502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829817	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829817	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829817	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	46644084	0	0
T1	1558	128	0	0
T2	338721	667	0	0
T3	3135	128	0	0
T4	150432	60615	0	0
T5	114622	13024	0	0
T12	1062	268	0	0
T13	609	176	0	0
T17	3636	512	0	0
T18	2686	128	0	0
T19	3084	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	117039614	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22834	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829817	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829817	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	117039614	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22834	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T29
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T13,T29
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T29

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T29
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T29

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T13,T29

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385025276	384222502	0	0
CheckNGreaterZero_A	1036	1036	0	0
GntImpliesReady_A	385025276	110829823	0	0
GntImpliesValid_A	385025276	110829823	0	0
GrantKnown_A	385025276	384222502	0	0
IdxKnown_A	385025276	384222502	0	0
IndexIsCorrect_A	385025276	110829823	0	0
NoReadyValidNoGrant_A	385025276	46644005	0	0
Priority_A	385025276	117039699	0	0
ReadyAndValidImplyGrant_A	385025276	110829823	0	0
ReqAndReadyImplyGrant_A	385025276	110829823	0	0
ReqImpliesValid_A	385025276	117039699	0	0
ValidKnown_A	385025276	384222502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829823	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829823	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829823	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	46644005	0	0
T1	1558	128	0	0
T2	338721	667	0	0
T3	3135	128	0	0
T4	150432	60615	0	0
T5	114622	13024	0	0
T12	1062	268	0	0
T13	609	176	0	0
T17	3636	512	0	0
T18	2686	128	0	0
T19	3084	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	117039699	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22834	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829823	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	110829823	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22002	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	117039699	0	0
T1	1558	32	0	0
T2	338721	140615	0	0
T3	3135	32	0	0
T4	150432	22834	0	0
T5	114622	48835	0	0
T12	1062	67	0	0
T13	609	50	0	0
T17	3636	146	0	0
T18	2686	292	0	0
T19	3084	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
1	0	Covered	T4,T14,T29

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T14,T29
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T14,T29
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T29
1	0	Covered	T1,T2,T18
1	1	Covered	T4,T14,T29

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T29
1	1	Covered	T1,T2,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T29
1	1	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T14,T29

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T14,T29

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385025276	384222502	0	0
CheckNGreaterZero_A	1036	1036	0	0
GntImpliesReady_A	385025276	90880108	0	0
GntImpliesValid_A	385025276	90880108	0	0
GrantKnown_A	385025276	384222502	0	0
IdxKnown_A	385025276	384222502	0	0
IndexIsCorrect_A	385025276	90880108	0	0
NoReadyValidNoGrant_A	385025276	42373969	0	0
Priority_A	385025276	96888366	0	0
ReadyAndValidImplyGrant_A	385025276	90880108	0	0
ReqAndReadyImplyGrant_A	385025276	90880108	0	0
ReqImpliesValid_A	385025276	96888366	0	0
ValidKnown_A	385025276	384222502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880108	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880108	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880108	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	42373969	0	0
T2	338721	776	0	0
T3	3135	0	0	0
T4	150432	54671	0	0
T5	114622	0	0	0
T6	0	667	0	0
T7	0	12467	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	83	0	0
T17	3636	0	0	0
T18	2686	33	0	0
T19	3084	0	0	0
T29	0	40	0	0
T31	0	48	0	0
T32	0	174	0	0
T37	0	25606	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	96888366	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	20948	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	17205	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880108	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880108	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	96888366	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	20948	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	17205	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
1	0	Covered	T4,T14,T29

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T14,T29
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T14,T29
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T29
1	0	Covered	T1,T2,T18
1	1	Covered	T4,T14,T29

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T29
1	1	Covered	T1,T2,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T29
1	1	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T14,T29

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T14,T29

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385025276	384222502	0	0
CheckNGreaterZero_A	1036	1036	0	0
GntImpliesReady_A	385025276	90880083	0	0
GntImpliesValid_A	385025276	90880083	0	0
GrantKnown_A	385025276	384222502	0	0
IdxKnown_A	385025276	384222502	0	0
IndexIsCorrect_A	385025276	90880083	0	0
NoReadyValidNoGrant_A	385025276	42374004	0	0
Priority_A	385025276	96888306	0	0
ReadyAndValidImplyGrant_A	385025276	90880083	0	0
ReqAndReadyImplyGrant_A	385025276	90880083	0	0
ReqImpliesValid_A	385025276	96888306	0	0
ValidKnown_A	385025276	384222502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880083	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880083	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880083	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	42374004	0	0
T2	338721	776	0	0
T3	3135	0	0	0
T4	150432	54671	0	0
T5	114622	0	0	0
T6	0	667	0	0
T7	0	12467	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	83	0	0
T17	3636	0	0	0
T18	2686	33	0	0
T19	3084	0	0	0
T29	0	40	0	0
T31	0	48	0	0
T32	0	174	0	0
T37	0	25606	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	96888306	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	20948	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	17205	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880083	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	90880083	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	19930	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	10085	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	96888306	0	0
T1	1558	169	0	0
T2	338721	141569	0	0
T3	3135	0	0	0
T4	150432	20948	0	0
T5	114622	0	0	0
T6	0	145156	0	0
T7	0	17205	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	0	32	0	0
T17	3636	0	0	0
T18	2686	21	0	0
T19	3084	0	0	0
T29	0	10	0	0
T31	0	18	0	0
T32	0	72	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0