Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	95.38		100.00	96.36	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	98.35	100.00	95.38		100.00	96.36	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	98.35	100.00	95.38		100.00	96.36	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	95.38		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	95.38	100.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.40	98.88	95.28		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	95.38		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.81	100.00	95.38	95.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	96.63	84.91		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	62	95.38
Logical	65	62	95.38
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T180,T183
1	0	Covered	T179,T180,T183

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T179,T180,T183

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T180,T183
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T6

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T6,T47

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T47

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T6

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T6

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T29,T31

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T31
1	1	Covered	T5,T29,T31

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T31
1	1	Covered	T5,T29,T31

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T29,T31
StCalcMask	237	Covered	T5,T29,T31
StCalcPlainEcc	215	Covered	T1,T2,T5
StDisabled	193	Covered	T12,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T5
StPostPack	218	Covered	T1,T2,T6
StPrePack	195	Covered	T2,T6,T47
StReqFlash	237	Covered	T1,T2,T5
StScrambleData	244	Covered	T5,T29,T31
StWaitFlash	270	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T29,T31
StCalcMask->StScrambleData	244	Covered	T5,T29,T31
StCalcPlainEcc->StCalcMask	237	Covered	T5,T29,T31
StCalcPlainEcc->StReqFlash	237	Covered	T1,T2,T6
StIdle->StDisabled	193	Covered	T12,T13,T14
StIdle->StPackData	197	Covered	T1,T2,T5
StIdle->StPrePack	195	Covered	T2,T6,T47
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T5
StPackData->StPostPack	218	Covered	T1,T2,T6
StPostPack->StCalcPlainEcc	231	Covered	T1,T2,T6
StPrePack->StPackData	205	Covered	T2,T6,T47
StReqFlash->StIdle	273	Covered	T1,T2,T5
StReqFlash->StWaitFlash	270	Covered	T1,T2,T5
StScrambleData->StCalcEcc	252	Covered	T5,T29,T31
StWaitFlash->StIdle	280	Covered	T1,T2,T5

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T47
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T47
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T29,T31
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T29,T31
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T29,T31
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T29,T31
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T29,T31
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T29,T31
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	Covered	T5,T29,T31
0	0	0	1	-	Covered	T5,T29,T31
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	770050552	2443158	0	0
PostPackRule_A	770050552	1845	0	0
PrePackRule_A	770050552	1228	0	0
WidthCheck_A	2072	2072	0	0
u_state_regs_A	770050552	768445004	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770050552	2443158	0	0
T1	1558	1	0	0
T2	677442	74	0	0
T3	6270	0	0	0
T4	300864	0	0	0
T5	229244	101	0	0
T6	0	75	0	0
T12	2124	0	0	0
T13	1218	0	0	0
T14	710	0	0	0
T17	7272	0	0	0
T18	5372	0	0	0
T19	6168	0	0	0
T27	0	65938	0	0
T29	0	1	0	0
T30	0	39	0	0
T31	0	2	0	0
T34	0	573	0	0
T47	0	4	0	0
T68	0	5	0	0
T69	0	146	0	0
T233	0	666	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770050552	1845	0	0
T1	1558	1	0	0
T2	677442	49	0	0
T3	6270	0	0	0
T4	300864	0	0	0
T5	229244	0	0	0
T6	0	52	0	0
T12	2124	0	0	0
T13	1218	0	0	0
T14	710	0	0	0
T17	7272	0	0	0
T18	5372	0	0	0
T19	6168	0	0	0
T27	0	10	0	0
T30	0	23	0	0
T38	0	11	0	0
T47	0	4	0	0
T61	0	12	0	0
T68	0	2	0	0
T128	0	1	0	0
T130	0	5	0	0
T196	0	3	0	0
T236	0	36	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770050552	1228	0	0
T2	677442	23	0	0
T3	6270	0	0	0
T4	300864	0	0	0
T5	229244	0	0	0
T6	0	28	0	0
T12	2124	0	0	0
T13	1218	0	0	0
T14	1420	0	0	0
T17	7272	0	0	0
T18	5372	0	0	0
T19	6168	0	0	0
T27	0	7	0	0
T30	0	18	0	0
T38	0	7	0	0
T47	0	3	0	0
T61	0	9	0	0
T68	0	1	0	0
T128	0	1	0	0
T130	0	2	0	0
T196	0	1	0	0
T209	0	6	0	0
T236	0	18	0	0
T237	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2072	2072	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770050552	768445004	0	0
T1	3116	2940	0	0
T2	677442	677260	0	0
T3	6270	6126	0	0
T4	300864	300594	0	0
T5	229244	218564	0	0
T12	2124	1676	0	0
T13	1218	1096	0	0
T17	7272	5804	0	0
T18	5372	5234	0	0
T19	6168	6020	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	62	95.38
Logical	65	62	95.38
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T180,T183
1	0	Covered	T179,T180,T183

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T179,T180,T183

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T180,T183
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T6,T47

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T6,T47

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T47

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T6,T47

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T47

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T6,T47
1	Covered	T5,T29,T31

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T31
1	1	Covered	T5,T29,T31

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T29,T31
1	1	Covered	T5,T29,T31

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T29,T31
StCalcMask	237	Covered	T5,T29,T31
StCalcPlainEcc	215	Covered	T2,T5,T6
StDisabled	193	Covered	T12,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T2,T5,T6
StPostPack	218	Covered	T2,T6,T47
StPrePack	195	Covered	T2,T6,T47
StReqFlash	237	Covered	T2,T5,T6
StScrambleData	244	Covered	T5,T29,T31
StWaitFlash	270	Covered	T2,T5,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T29,T31
StCalcMask->StScrambleData	244	Covered	T5,T29,T31
StCalcPlainEcc->StCalcMask	237	Covered	T5,T29,T31
StCalcPlainEcc->StReqFlash	237	Covered	T2,T6,T47
StIdle->StDisabled	193	Covered	T12,T13,T14
StIdle->StPackData	197	Covered	T2,T5,T6
StIdle->StPrePack	195	Covered	T2,T6,T47
StPackData->StCalcPlainEcc	215	Covered	T2,T5,T6
StPackData->StPostPack	218	Covered	T2,T6,T47
StPostPack->StCalcPlainEcc	231	Covered	T2,T6,T47
StPrePack->StPackData	205	Covered	T2,T6,T47
StReqFlash->StIdle	273	Covered	T2,T5,T6
StReqFlash->StWaitFlash	270	Covered	T2,T5,T6
StScrambleData->StCalcEcc	252	Covered	T5,T29,T31
StWaitFlash->StIdle	280	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T47
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T47
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T47
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T6,T47
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T29,T31
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T6,T47
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T29,T31
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T29,T31
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T29,T31
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T29,T31
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T29,T31
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T5,T6
0	0	1	-	-	Covered	T5,T29,T31
0	0	0	1	-	Covered	T5,T29,T31
0	0	0	0	1	Covered	T2,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	385025276	1244357	0	0
PostPackRule_A	385025276	939	0	0
PrePackRule_A	385025276	638	0	0
WidthCheck_A	1036	1036	0	0
u_state_regs_A	385025276	384222502	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	1244357	0	0
T2	338721	37	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	101	0	0
T6	0	39	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	33159	0	0
T29	0	1	0	0
T30	0	16	0	0
T31	0	2	0	0
T47	0	3	0	0
T68	0	3	0	0
T69	0	69	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	939	0	0
T2	338721	23	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	0	0	0
T6	0	28	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	2	0	0
T30	0	11	0	0
T38	0	4	0	0
T47	0	3	0	0
T68	0	2	0	0
T128	0	1	0	0
T196	0	3	0	0
T236	0	20	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	638	0	0
T2	338721	10	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	0	0	0
T6	0	15	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	3	0	0
T30	0	10	0	0
T38	0	4	0	0
T47	0	3	0	0
T68	0	1	0	0
T128	0	1	0	0
T196	0	1	0	0
T236	0	10	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	62	95.38
Logical	65	62	95.38
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20
1	0	Covered	T10,T20

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T10,T20

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20
1	0	Covered	T1,T2,T18

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T6,T30

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T6,T30

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T30
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T6

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T27,T156,T42

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T6,T47
1	Covered	T1,T2,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T29
1	0	Covered	T27,T156,T42
1	1	Covered	T27,T156,T42

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T29
1	0	Covered	T27,T156,T42
1	1	Covered	T27,T156,T42

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T4

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T42,T43,T148
StCalcMask	237	Covered	T42,T43,T148
StCalcPlainEcc	215	Covered	T1,T2,T6
StDisabled	193	Covered	T12,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T6
StPostPack	218	Covered	T1,T2,T6
StPrePack	195	Covered	T2,T6,T30
StReqFlash	237	Covered	T1,T2,T6
StScrambleData	244	Covered	T42,T43,T148
StWaitFlash	270	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T42,T43,T148
StCalcMask->StScrambleData	244	Covered	T42,T43,T148
StCalcPlainEcc->StCalcMask	237	Covered	T42,T43,T148
StCalcPlainEcc->StReqFlash	237	Covered	T1,T2,T6
StIdle->StDisabled	193	Covered	T12,T13,T14
StIdle->StPackData	197	Covered	T1,T2,T6
StIdle->StPrePack	195	Covered	T2,T6,T30
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T6
StPackData->StPostPack	218	Covered	T1,T2,T6
StPostPack->StCalcPlainEcc	231	Covered	T1,T2,T6
StPrePack->StPackData	205	Covered	T2,T6,T30
StReqFlash->StIdle	273	Covered	T1,T2,T6
StReqFlash->StWaitFlash	270	Covered	T1,T2,T6
StScrambleData->StCalcEcc	252	Covered	T42,T43,T148
StWaitFlash->StIdle	280	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T6
0	1	Covered	T2,T18,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T30
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T30
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T156,T42
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T27,T156,T42
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T27,T156,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T156,T42
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T27,T156,T42
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T156,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T6,T47
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T6
0	0	1	-	-	Covered	T27,T156,T42
0	0	0	1	-	Covered	T27,T156,T42
0	0	0	0	1	Covered	T1,T2,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	385025276	1198801	0	0
PostPackRule_A	385025276	906	0	0
PrePackRule_A	385025276	590	0	0
WidthCheck_A	1036	1036	0	0
u_state_regs_A	385025276	384222502	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	1198801	0	0
T1	1558	1	0	0
T2	338721	37	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	0	0	0
T6	0	36	0	0
T12	1062	0	0	0
T13	609	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	32779	0	0
T30	0	23	0	0
T34	0	573	0	0
T47	0	1	0	0
T68	0	2	0	0
T69	0	77	0	0
T233	0	666	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	906	0	0
T1	1558	1	0	0
T2	338721	26	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	0	0	0
T6	0	24	0	0
T12	1062	0	0	0
T13	609	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	8	0	0
T30	0	12	0	0
T38	0	7	0	0
T47	0	1	0	0
T61	0	12	0	0
T130	0	5	0	0
T236	0	16	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	590	0	0
T2	338721	13	0	0
T3	3135	0	0	0
T4	150432	0	0	0
T5	114622	0	0	0
T6	0	13	0	0
T12	1062	0	0	0
T13	609	0	0	0
T14	710	0	0	0
T17	3636	0	0	0
T18	2686	0	0	0
T19	3084	0	0	0
T27	0	4	0	0
T30	0	8	0	0
T38	0	3	0	0
T61	0	9	0	0
T130	0	2	0	0
T209	0	6	0	0
T236	0	8	0	0
T237	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036	1036	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385025276	384222502	0	0
T1	1558	1470	0	0
T2	338721	338630	0	0
T3	3135	3063	0	0
T4	150432	150297	0	0
T5	114622	109282	0	0
T12	1062	838	0	0
T13	609	548	0	0
T17	3636	2902	0	0
T18	2686	2617	0	0
T19	3084	3010	0	0