SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.71 | 97.12 | 94.40 | 98.44 | 100.00 | 98.57 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.16 | 99.17 | 92.71 | 92.11 | 96.81 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.41 | 88.24 | 83.33 | 57.14 | 83.33 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.71 | 97.12 | 94.40 | 98.44 | 100.00 | 98.57 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
74.63 | 88.24 | 94.44 | 57.14 | 83.33 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.22 | 97.67 | 88.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10360 | 10360 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21426 |
gen_no_flops.OutputDelay_A | 758705402 | 757099854 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10360 | 10360 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T13 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 15580 | 14700 | 0 | 0 |
T2 | 3387210 | 3386300 | 0 | 0 |
T3 | 31350 | 30630 | 0 | 0 |
T4 | 1504320 | 1502970 | 0 | 0 |
T5 | 1146220 | 1092820 | 0 | 0 |
T12 | 10620 | 8380 | 0 | 0 |
T13 | 5933 | 5323 | 0 | 0 |
T17 | 36360 | 29020 | 0 | 0 |
T18 | 26860 | 26170 | 0 | 0 |
T19 | 30840 | 30100 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21426 |
T1 | 12464 | 11736 | 0 | 24 |
T2 | 2709768 | 2709016 | 0 | 24 |
T3 | 25080 | 24480 | 0 | 24 |
T4 | 1203456 | 1202328 | 0 | 24 |
T5 | 916976 | 872552 | 0 | 24 |
T12 | 8496 | 6632 | 0 | 24 |
T13 | 4715 | 4206 | 0 | 21 |
T17 | 29088 | 23000 | 0 | 24 |
T18 | 21488 | 20912 | 0 | 24 |
T19 | 24672 | 24056 | 0 | 24 |
T59 | 0 | 0 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 758705402 | 757099854 | 0 | 0 |
T1 | 3116 | 2940 | 0 | 0 |
T2 | 677442 | 677260 | 0 | 0 |
T3 | 6270 | 6126 | 0 | 0 |
T4 | 300864 | 300594 | 0 | 0 |
T5 | 229244 | 218564 | 0 | 0 |
T12 | 2124 | 1676 | 0 | 0 |
T13 | 1218 | 1096 | 0 | 0 |
T17 | 7272 | 5804 | 0 | 0 |
T18 | 5372 | 5234 | 0 | 0 |
T19 | 6168 | 6020 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352772 | 378549998 | 0 | 0 |
gen_flops.OutputDelay_A | 379352772 | 378518573 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378549998 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352772 | 378518573 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352701 | 378549927 | 0 | 0 |
gen_no_flops.OutputDelay_A | 379352701 | 378549927 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378549927 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378549927 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379328325 | 378525551 | 0 | 0 |
gen_flops.OutputDelay_A | 379328325 | 378494276 | 0 | 2547 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379328325 | 378525551 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 452 | 391 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379328325 | 378494276 | 0 | 2547 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 452 | 391 | 0 | 0 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
T59 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352701 | 378549927 | 0 | 0 |
gen_no_flops.OutputDelay_A | 379352701 | 378549927 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378549927 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378549927 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1036 | 1036 | 0 | 0 |
OutputsKnown_A | 379352701 | 378549927 | 0 | 0 |
gen_flops.OutputDelay_A | 379352701 | 378518517 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1036 | 1036 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378549927 | 0 | 0 |
T1 | 1558 | 1470 | 0 | 0 |
T2 | 338721 | 338630 | 0 | 0 |
T3 | 3135 | 3063 | 0 | 0 |
T4 | 150432 | 150297 | 0 | 0 |
T5 | 114622 | 109282 | 0 | 0 |
T12 | 1062 | 838 | 0 | 0 |
T13 | 609 | 548 | 0 | 0 |
T17 | 3636 | 2902 | 0 | 0 |
T18 | 2686 | 2617 | 0 | 0 |
T19 | 3084 | 3010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379352701 | 378518517 | 0 | 2697 |
T1 | 1558 | 1467 | 0 | 3 |
T2 | 338721 | 338627 | 0 | 3 |
T3 | 3135 | 3060 | 0 | 3 |
T4 | 150432 | 150291 | 0 | 3 |
T5 | 114622 | 109069 | 0 | 3 |
T12 | 1062 | 829 | 0 | 3 |
T13 | 609 | 545 | 0 | 3 |
T17 | 3636 | 2875 | 0 | 3 |
T18 | 2686 | 2614 | 0 | 3 |
T19 | 3084 | 3007 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |