Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	31101999	1		T1	62		T2	34153		T3	5181
full_word	7622406	1		T1	44		T2	2756		T3	3174

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	38724145	1		T1	106		T2	36909		T3	8355
auto[TlIntgErrCmd]	92	1		T68	4		T70	8		T216	3
auto[TlIntgErrData]	101	1		T68	4		T70	5		T216	6
auto[TlIntgErrBoth]	67	1		T68	2		T70	7		T216	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34311296	1		T1	59		T2	34986		T3	4978
auto[1]	4413109	1		T1	47		T2	1923		T3	3377

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30471947	1		T1	58		T2	33885		T3	4861
auto[TlIntgErrNone]	partial	auto[1]	629810	1		T1	4		T2	268		T3	320
auto[TlIntgErrNone]	full_word	auto[0]	3839231	1		T1	1		T2	1101		T3	117
auto[TlIntgErrNone]	full_word	auto[1]	3783157	1		T1	43		T2	1655		T3	3057
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T68	2		T70	4		T238	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T68	2		T70	4		T216	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T238	1		T274	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T216	1		T363	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T68	1		T70	3		T216	3
auto[TlIntgErrData]	partial	auto[1]	44	1		T68	3		T70	2		T216	3
auto[TlIntgErrData]	full_word	auto[0]	1	1		T238	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T358	1		T364	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	21	1		T70	2		T238	2		T217	1
auto[TlIntgErrBoth]	partial	auto[1]	39	1		T68	2		T70	5		T238	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T238	1		T365	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T216	1		T319	1		T364	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21424	1		T68	9		T70	16		T201	181
full_word	4076282	1		T4	6		T18	16623		T21	18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4097463	1		T4	6		T18	16623		T21	18
auto[TlIntgErrCmd]	71	1		T68	4		T70	5		T216	1
auto[TlIntgErrData]	91	1		T68	4		T70	10		T216	6
auto[TlIntgErrBoth]	81	1		T68	1		T70	2		T216	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4071467	1		T4	6		T18	16623		T21	18
auto[1]	26239	1		T68	5		T70	10		T201	260

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1510	1		T201	8		T214	37		T215	19
auto[TlIntgErrNone]	partial	auto[1]	19681	1		T201	173		T214	410		T215	182
auto[TlIntgErrNone]	full_word	auto[0]	4069861	1		T4	6		T18	16623		T21	18
auto[TlIntgErrNone]	full_word	auto[1]	6411	1		T201	87		T214	134		T215	64
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T68	1		T70	3		T238	3
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T68	3		T70	2		T216	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T366	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T361	1		T367	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1		T68	2		T70	3		T216	2
auto[TlIntgErrData]	partial	auto[1]	49	1		T68	2		T70	6		T216	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T70	1		T360	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T216	1		T363	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T68	1		T216	2		T238	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T70	2		T216	1		T238	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T365	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T300	1		T366	1		-	-