Unified Coverage Report :: Module :: tlul_data_integ_dec

Module : tlul_data_integ_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec	100.00	100.00
tb.dut.u_flash_hw_if.u_data_intg_chk	100.00	100.00
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec	100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk	100.00	100.00

---

Module Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_data_intg_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.33	100.00	90.62		92.11	98.94	100.00	u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.38	100.00	96.92		100.00	100.00	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00		95.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.38	100.00	96.92		100.00	100.00	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	95.00			95.00

Line Coverage for Module : tlul_data_integ_dec

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1