Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1437991264	1434661964	0	0
CheckNGreaterZero_A	4092	4092	0	0
GntImpliesReady_A	1437991264	416093573	0	0
GntImpliesValid_A	1437991264	416093573	0	0
GrantKnown_A	1437991264	1434661964	0	0
IdxKnown_A	1437991264	1434661964	0	0
IndexIsCorrect_A	1437991264	416093573	0	0
NoReadyValidNoGrant_A	1437991264	177357216	0	0
Priority_A	1437991264	440226323	0	0
ReadyAndValidImplyGrant_A	1437991264	416093573	0	0
ReqAndReadyImplyGrant_A	1437991264	416093573	0	0
ReqImpliesValid_A	1437991264	440226323	0	0
ValidKnown_A	1437991264	1434661964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	1434661964	0	0
T1	4312	3528	0	0
T2	1036320	1036084	0	0
T3	258864	258220	0	0
T4	8520	7984	0	0
T5	5928	5528	0	0
T11	3956	3656	0	0
T16	2194632	2194352	0	0
T17	4996	4200	0	0
T18	293336	292864	0	0
T19	14972	14720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4092	4092	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	416093573	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	46814	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	416093573	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	46814	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	1434661964	0	0
T1	4312	3528	0	0
T2	1036320	1036084	0	0
T3	258864	258220	0	0
T4	8520	7984	0	0
T5	5928	5528	0	0
T11	3956	3656	0	0
T16	2194632	2194352	0	0
T17	4996	4200	0	0
T18	293336	292864	0	0
T19	14972	14720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	1434661964	0	0
T1	4312	3528	0	0
T2	1036320	1036084	0	0
T3	258864	258220	0	0
T4	8520	7984	0	0
T5	5928	5528	0	0
T11	3956	3656	0	0
T16	2194632	2194352	0	0
T17	4996	4200	0	0
T18	293336	292864	0	0
T19	14972	14720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	416093573	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	46814	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	177357216	0	0
T1	2156	536	0	0
T2	1036320	3202	0	0
T3	258864	424	0	0
T4	8520	828	0	0
T5	5928	256	0	0
T11	3956	256	0	0
T16	2194632	16160	0	0
T17	4996	520	0	0
T18	293336	132852	0	0
T19	14972	256	0	0
T21	19640	264	0	0
T29	0	84	0	0
T30	0	20	0	0
T42	0	540	0	0
T50	0	54	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	440226323	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	49852	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	416093573	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	46814	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	416093573	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	46814	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	440226323	0	0
T1	2156	134	0	0
T2	1036320	449158	0	0
T3	258864	42494	0	0
T4	8520	834	0	0
T5	5928	736	0	0
T11	3956	584	0	0
T16	2194632	144628	0	0
T17	4996	130	0	0
T18	293336	49852	0	0
T19	14972	64	0	0
T21	19640	3762	0	0
T29	0	156	0	0
T30	0	8	0	0
T55	0	211872	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437991264	1434661964	0	0
T1	4312	3528	0	0
T2	1036320	1036084	0	0
T3	258864	258220	0	0
T4	8520	7984	0	0
T5	5928	5528	0	0
T11	3956	3656	0	0
T16	2194632	2194352	0	0
T17	4996	4200	0	0
T18	293336	292864	0	0
T19	14972	14720	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	359497816	358665491	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	359497816	112638068	0	0
GntImpliesValid_A	359497816	112638068	0	0
GrantKnown_A	359497816	358665491	0	0
IdxKnown_A	359497816	358665491	0	0
IndexIsCorrect_A	359497816	112638068	0	0
NoReadyValidNoGrant_A	359497816	46540332	0	0
Priority_A	359497816	118595452	0	0
ReadyAndValidImplyGrant_A	359497816	112638068	0	0
ReqAndReadyImplyGrant_A	359497816	112638068	0	0
ReqImpliesValid_A	359497816	118595452	0	0
ValidKnown_A	359497816	358665491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	46540332	0	0
T1	1078	268	0	0
T2	259080	767	0	0
T3	64716	166	0	0
T4	2130	380	0	0
T5	1482	128	0	0
T11	989	128	0	0
T16	548658	4117	0	0
T17	1249	260	0	0
T18	73334	42545	0	0
T19	3743	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	118595452	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15902	0	0
T19	3743	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	118595452	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15902	0	0
T19	3743	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	359497816	358665491	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	359497816	112638068	0	0
GntImpliesValid_A	359497816	112638068	0	0
GrantKnown_A	359497816	358665491	0	0
IdxKnown_A	359497816	358665491	0	0
IndexIsCorrect_A	359497816	112638068	0	0
NoReadyValidNoGrant_A	359497816	46540332	0	0
Priority_A	359497816	118595452	0	0
ReadyAndValidImplyGrant_A	359497816	112638068	0	0
ReqAndReadyImplyGrant_A	359497816	112638068	0	0
ReqImpliesValid_A	359497816	118595452	0	0
ValidKnown_A	359497816	358665491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	46540332	0	0
T1	1078	268	0	0
T2	259080	767	0	0
T3	64716	166	0	0
T4	2130	380	0	0
T5	1482	128	0	0
T11	989	128	0	0
T16	548658	4117	0	0
T17	1249	260	0	0
T18	73334	42545	0	0
T19	3743	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	118595452	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15902	0	0
T19	3743	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	112638068	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15537	0	0
T19	3743	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	118595452	0	0
T1	1078	67	0	0
T2	259080	15995	0	0
T3	64716	11378	0	0
T4	2130	404	0	0
T5	1482	32	0	0
T11	989	292	0	0
T16	548658	28680	0	0
T17	1249	65	0	0
T18	73334	15902	0	0
T19	3743	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T18,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T18,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	359497816	358665491	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	359497816	95408749	0	0
GntImpliesValid_A	359497816	95408749	0	0
GrantKnown_A	359497816	358665491	0	0
IdxKnown_A	359497816	358665491	0	0
IndexIsCorrect_A	359497816	95408749	0	0
NoReadyValidNoGrant_A	359497816	42138276	0	0
Priority_A	359497816	101517740	0	0
ReadyAndValidImplyGrant_A	359497816	95408749	0	0
ReqAndReadyImplyGrant_A	359497816	95408749	0	0
ReqImpliesValid_A	359497816	101517740	0	0
ValidKnown_A	359497816	358665491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408749	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408749	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408749	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	42138276	0	0
T2	259080	834	0	0
T3	64716	46	0	0
T4	2130	34	0	0
T5	1482	0	0	0
T11	989	0	0	0
T16	548658	3963	0	0
T17	1249	0	0	0
T18	73334	23881	0	0
T19	3743	0	0	0
T21	9820	132	0	0
T29	0	42	0	0
T30	0	10	0	0
T42	0	270	0	0
T50	0	27	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	101517740	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	9024	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408749	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408749	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	101517740	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	9024	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T18,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T18,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T18,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	359497816	358665491	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	359497816	95408688	0	0
GntImpliesValid_A	359497816	95408688	0	0
GrantKnown_A	359497816	358665491	0	0
IdxKnown_A	359497816	358665491	0	0
IndexIsCorrect_A	359497816	95408688	0	0
NoReadyValidNoGrant_A	359497816	42138276	0	0
Priority_A	359497816	101517679	0	0
ReadyAndValidImplyGrant_A	359497816	95408688	0	0
ReqAndReadyImplyGrant_A	359497816	95408688	0	0
ReqImpliesValid_A	359497816	101517679	0	0
ValidKnown_A	359497816	358665491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408688	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408688	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408688	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	42138276	0	0
T2	259080	834	0	0
T3	64716	46	0	0
T4	2130	34	0	0
T5	1482	0	0	0
T11	989	0	0	0
T16	548658	3963	0	0
T17	1249	0	0	0
T18	73334	23881	0	0
T19	3743	0	0	0
T21	9820	132	0	0
T29	0	42	0	0
T30	0	10	0	0
T42	0	270	0	0
T50	0	27	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	101517679	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	9024	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408688	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	95408688	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	7870	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	101517679	0	0
T2	259080	208584	0	0
T3	64716	9869	0	0
T4	2130	13	0	0
T5	1482	336	0	0
T11	989	0	0	0
T16	548658	43634	0	0
T17	1249	0	0	0
T18	73334	9024	0	0
T19	3743	0	0	0
T21	9820	1881	0	0
T29	0	78	0	0
T30	0	4	0	0
T55	0	105936	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0