Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi	100.00	100.00				100.00	100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.86	35.71					100.00	gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.86	35.71					100.00	gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
71.43	42.86					100.00	gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
71.43	42.86					100.00	gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.86	35.71					100.00	gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.86	35.71					100.00	gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
71.43	42.86					100.00	gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
71.43	42.86					100.00	gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sec_buf.u_prim_sec_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12936	10584	0	0
T2	3108960	3108252	0	0
T3	776592	774660	0	0
T4	25560	23952	0	0
T5	17784	16584	0	0
T11	11868	10968	0	0
T16	6583896	6583056	0	0
T17	14988	12600	0	0
T18	880008	878592	0	0
T19	44916	44160	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	359497874	358665549	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497874	358665549	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0